2 This file implement the MMC Host Protocol for the ARM PrimeCell PL180.
4 Copyright (c) 2011, ARM Limited. All rights reserved.
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #include <Library/DevicePathLib.h>
19 #include <Library/BaseMemoryLib.h>
21 EFI_MMC_HOST_PROTOCOL
*gpMmcHost
;
26 #define MMCI0_BLOCKLEN 512
27 #define MMCI0_POW2_BLOCKLEN 9
28 #define MMCI0_TIMEOUT 1000
35 return ((MmioRead32(MCI_POWER_CONTROL_REG
) & 0x3) == MCI_POWER_ON
);
43 MCI_TRACE("MciInitialize()");
52 return (MmioRead32(FixedPcdGet32(PcdPL180SysMciRegAddress
)) & 1);
60 return (MmioRead32(FixedPcdGet32(PcdPL180SysMciRegAddress
)) & 2);
64 //Note: This function has been commented out because it is not used yet.
65 // This function could be used to remove the hardcoded BlockLen used
66 // in MciPrepareDataPath
68 // Convert block size to 2^n
81 Loop
= (Loop
>> 1) & 0xFFFF;
83 } while (Pow2BlockLen
&& (!(Loop
& BlockLen
)));
91 IN UINTN TransferDirection
94 // Set Data Length & Data Timer
95 MmioWrite32(MCI_DATA_TIMER_REG
,0xFFFFFFF);
96 MmioWrite32(MCI_DATA_LENGTH_REG
,MMCI0_BLOCKLEN
);
99 //Note: we are using a hardcoded BlockLen (=512). If we decide to use a variable size, we could
100 // compute the pow2 of BlockLen with the above function GetPow2BlockLen()
101 MmioWrite32(MCI_DATA_CTL_REG
, MCI_DATACTL_ENABLE
| MCI_DATACTL_DMA_ENABLE
| TransferDirection
| (MMCI0_POW2_BLOCKLEN
<< 4));
103 MmioWrite32(MCI_DATA_CTL_REG
, MCI_DATACTL_ENABLE
| MCI_DATACTL_DMA_ENABLE
| TransferDirection
| MCI_DATACTL_STREAM_TRANS
);
118 RetVal
= EFI_SUCCESS
;
120 if ((MmcCmd
== MMC_CMD17
) || (MmcCmd
== MMC_CMD11
)) {
121 MciPrepareDataPath(MCI_DATACTL_CARD_TO_CONT
);
122 } else if ((MmcCmd
== MMC_CMD24
) || (MmcCmd
== MMC_CMD20
)) {
123 MciPrepareDataPath(MCI_DATACTL_CONT_TO_CARD
);
126 // Create Command for PL180
127 Cmd
= (MMC_GET_INDX(MmcCmd
) & INDX_MASK
) | MCI_CPSM_ENABLED
;
128 if (MmcCmd
& MMC_CMD_WAIT_RESPONSE
) {
129 Cmd
|= MCI_CPSM_WAIT_RESPONSE
;
132 if (MmcCmd
& MMC_CMD_LONG_RESPONSE
) {
133 Cmd
|= MCI_CPSM_LONG_RESPONSE
;
136 // Clear Status register static flags
137 MmioWrite32(MCI_CLEAR_STATUS_REG
,0x7FF);
139 //Write to command argument register
140 MmioWrite32(MCI_ARGUMENT_REG
,Argument
);
142 //Write to command register
143 MmioWrite32(MCI_COMMAND_REG
,Cmd
);
145 if (Cmd
& MCI_CPSM_WAIT_RESPONSE
) {
146 Status
= MmioRead32(MCI_STATUS_REG
);
147 while (!(Status
& (MCI_STATUS_CMD_RESPEND
| MCI_STATUS_CMD_CMDCRCFAIL
| MCI_STATUS_CMD_CMDTIMEOUT
| MCI_STATUS_CMD_START_BIT_ERROR
))) {
148 Status
= MmioRead32(MCI_STATUS_REG
);
151 if ((Status
& MCI_STATUS_CMD_START_BIT_ERROR
)) {
152 DEBUG ((EFI_D_ERROR
, "MciSendCommand(CmdIndex:%d) Start bit Error! Response:0x%X Status:0x%x\n",(Cmd
& 0x3F),MmioRead32(MCI_RESPONSE0_REG
),Status
));
153 RetVal
= EFI_NO_RESPONSE
;
155 } else if ((Status
& MCI_STATUS_CMD_CMDTIMEOUT
)) {
156 //DEBUG ((EFI_D_ERROR, "MciSendCommand(CmdIndex:%d) TIMEOUT! Response:0x%X Status:0x%x\n",(Cmd & 0x3F),MmioRead32(MCI_RESPONSE0_REG),Status));
157 RetVal
= EFI_TIMEOUT
;
159 } else if ((!(MmcCmd
& MMC_CMD_NO_CRC_RESPONSE
)) && (Status
& MCI_STATUS_CMD_CMDCRCFAIL
)) {
160 // The CMD1 and response type R3 do not contain CRC. We should ignore the CRC failed Status.
161 RetVal
= EFI_CRC_ERROR
;
164 RetVal
= EFI_SUCCESS
;
168 Status
= MmioRead32(MCI_STATUS_REG
);
169 while (!(Status
& (MCI_STATUS_CMD_SENT
| MCI_STATUS_CMD_CMDCRCFAIL
| MCI_STATUS_CMD_CMDTIMEOUT
| MCI_STATUS_CMD_START_BIT_ERROR
))) {
170 Status
= MmioRead32(MCI_STATUS_REG
);
173 if ((Status
& MCI_STATUS_CMD_START_BIT_ERROR
)) {
174 DEBUG ((EFI_D_ERROR
, "MciSendCommand(CmdIndex:%d) Start bit Error! Response:0x%X Status:0x%x\n",(Cmd
& 0x3F),MmioRead32(MCI_RESPONSE0_REG
),Status
));
175 RetVal
= EFI_NO_RESPONSE
;
177 } else if ((Status
& MCI_STATUS_CMD_CMDTIMEOUT
)) {
178 //DEBUG ((EFI_D_ERROR, "MciSendCommand(CmdIndex:%d) TIMEOUT! Response:0x%X Status:0x%x\n",(Cmd & 0x3F),MmioRead32(MCI_RESPONSE0_REG),Status));
179 RetVal
= EFI_TIMEOUT
;
182 if ((!(MmcCmd
& MMC_CMD_NO_CRC_RESPONSE
)) && (Status
& MCI_STATUS_CMD_CMDCRCFAIL
)) {
183 // The CMD1 does not contain CRC. We should ignore the CRC failed Status.
184 RetVal
= EFI_CRC_ERROR
;
187 RetVal
= EFI_SUCCESS
;
193 //Disable Command Path
194 CmdCtrlReg
= MmioRead32(MCI_COMMAND_REG
);
195 MmioWrite32(MCI_COMMAND_REG
, (CmdCtrlReg
& ~MCI_CPSM_ENABLED
));
201 IN MMC_RESPONSE_TYPE Type
,
205 if (Buffer
== NULL
) {
206 return EFI_INVALID_PARAMETER
;
209 if ((Type
== MMC_RESPONSE_TYPE_R1
) || (Type
== MMC_RESPONSE_TYPE_R1b
) ||
210 (Type
== MMC_RESPONSE_TYPE_R3
) || (Type
== MMC_RESPONSE_TYPE_R6
) ||
211 (Type
== MMC_RESPONSE_TYPE_R7
))
213 Buffer
[0] = MmioRead32(MCI_RESPONSE3_REG
);
214 } else if (Type
== MMC_RESPONSE_TYPE_R2
) {
215 Buffer
[0] = MmioRead32(MCI_RESPONSE0_REG
);
216 Buffer
[1] = MmioRead32(MCI_RESPONSE1_REG
);
217 Buffer
[2] = MmioRead32(MCI_RESPONSE2_REG
);
218 Buffer
[3] = MmioRead32(MCI_RESPONSE3_REG
);
237 RetVal
= EFI_SUCCESS
;
239 // Read data from the RX FIFO
241 Finish
= MMCI0_BLOCKLEN
/ 4;
243 // Read the Status flags
244 Status
= MmioRead32(MCI_STATUS_REG
);
246 // Do eight reads if possible else a single read
247 if (Status
& MCI_STATUS_CMD_RXFIFOHALFFULL
) {
248 Buffer
[Loop
] = MmioRead32(MCI_FIFO_REG
);
250 Buffer
[Loop
] = MmioRead32(MCI_FIFO_REG
);
252 Buffer
[Loop
] = MmioRead32(MCI_FIFO_REG
);
254 Buffer
[Loop
] = MmioRead32(MCI_FIFO_REG
);
256 Buffer
[Loop
] = MmioRead32(MCI_FIFO_REG
);
258 Buffer
[Loop
] = MmioRead32(MCI_FIFO_REG
);
260 Buffer
[Loop
] = MmioRead32(MCI_FIFO_REG
);
262 Buffer
[Loop
] = MmioRead32(MCI_FIFO_REG
);
264 } else if (Status
& MCI_STATUS_CMD_RXDATAAVAILBL
) {
265 Buffer
[Loop
] = MmioRead32(MCI_FIFO_REG
);
268 //Check for error conditions and timeouts
269 if(Status
& MCI_STATUS_CMD_DATATIMEOUT
) {
270 DEBUG ((EFI_D_ERROR
, "MciReadBlockData(): TIMEOUT! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG
),Status
));
271 RetVal
= EFI_TIMEOUT
;
273 } else if(Status
& MCI_STATUS_CMD_DATACRCFAIL
) {
274 DEBUG ((EFI_D_ERROR
, "MciReadBlockData(): CRC Error! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG
),Status
));
275 RetVal
= EFI_CRC_ERROR
;
277 } else if(Status
& MCI_STATUS_CMD_START_BIT_ERROR
) {
278 DEBUG ((EFI_D_ERROR
, "MciReadBlockData(): Start-bit Error! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG
),Status
));
279 RetVal
= EFI_NO_RESPONSE
;
283 //clear RX over run flag
284 if(Status
& MCI_STATUS_CMD_RXOVERRUN
) {
285 MmioWrite32(MCI_CLEAR_STATUS_REG
, MCI_STATUS_CMD_RXOVERRUN
);
287 } while ((Loop
< Finish
));
290 MmioWrite32(MCI_CLEAR_STATUS_REG
, 0x7FF);
293 DataCtrlReg
= MmioRead32(MCI_DATA_CTL_REG
);
294 MmioWrite32(MCI_DATA_CTL_REG
, (DataCtrlReg
& 0xFE));
313 RetVal
= EFI_SUCCESS
;
315 // Write the data to the TX FIFO
317 Finish
= MMCI0_BLOCKLEN
/ 4;
318 Timer
= MMCI0_TIMEOUT
* 100;
320 // Read the Status flags
321 Status
= MmioRead32(MCI_STATUS_REG
);
323 // Do eight writes if possible else a single write
324 if (Status
& MCI_STATUS_CMD_TXFIFOHALFEMPTY
) {
325 MmioWrite32(MCI_FIFO_REG
, Buffer
[Loop
]);
327 MmioWrite32(MCI_FIFO_REG
, Buffer
[Loop
]);
329 MmioWrite32(MCI_FIFO_REG
, Buffer
[Loop
]);
331 MmioWrite32(MCI_FIFO_REG
, Buffer
[Loop
]);
333 MmioWrite32(MCI_FIFO_REG
, Buffer
[Loop
]);
335 MmioWrite32(MCI_FIFO_REG
, Buffer
[Loop
]);
337 MmioWrite32(MCI_FIFO_REG
, Buffer
[Loop
]);
339 MmioWrite32(MCI_FIFO_REG
, Buffer
[Loop
]);
341 } else if ((Status
& MCI_STATUS_CMD_TXFIFOEMPTY
)) {
342 MmioWrite32(MCI_FIFO_REG
, Buffer
[Loop
]);
345 //Check for error conditions and timeouts
346 if(Status
& MCI_STATUS_CMD_DATATIMEOUT
) {
347 DEBUG ((EFI_D_ERROR
, "MciWriteBlockData(): TIMEOUT! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG
),Status
));
348 RetVal
= EFI_TIMEOUT
;
350 } else if(Status
& MCI_STATUS_CMD_DATACRCFAIL
) {
351 DEBUG ((EFI_D_ERROR
, "MciWriteBlockData(): CRC Error! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG
),Status
));
352 RetVal
= EFI_CRC_ERROR
;
354 } else if(Status
& MCI_STATUS_CMD_TX_UNDERRUN
) {
355 DEBUG ((EFI_D_ERROR
, "MciWriteBlockData(): TX buffer Underrun! Response:0x%X Status:0x%x, Number of bytes written 0x%x\n",MmioRead32(MCI_RESPONSE0_REG
),Status
, Loop
));
356 RetVal
= EFI_BUFFER_TOO_SMALL
;
361 } while (Loop
< Finish
);
363 // Wait for FIFO to drain
364 Timer
= MMCI0_TIMEOUT
* 60;
365 Status
= MmioRead32(MCI_STATUS_REG
);
368 while (((Status
& MCI_STATUS_CMD_TXDONE
) != MCI_STATUS_CMD_TXDONE
) && Timer
) {
371 while (((Status
& MCI_STATUS_CMD_DATAEND
) != MCI_STATUS_CMD_DATAEND
) && Timer
) {
374 Status
= MmioRead32(MCI_STATUS_REG
);
379 DEBUG ((EFI_D_ERROR
, "MciWriteBlockData(): Data End timeout Number of bytes written 0x%x\n",Loop
));
385 MmioWrite32(MCI_CLEAR_STATUS_REG
, 0x7FF);
387 RetVal
= EFI_TIMEOUT
;
392 DataCtrlReg
= MmioRead32(MCI_DATA_CTL_REG
);
393 MmioWrite32(MCI_DATA_CTL_REG
, (DataCtrlReg
& 0xFE));
405 case MmcInvalidState
:
408 case MmcHwInitializationState
:
409 // If device already turn on then restart it
410 Data32
= MmioRead32(MCI_POWER_CONTROL_REG
);
411 if ((Data32
& 0x2) == MCI_POWER_UP
) {
412 MCI_TRACE("MciNotifyState(MmcHwInitializationState): TurnOff MCI");
415 MmioWrite32(MCI_CLOCK_CONTROL_REG
, 0);
416 MmioWrite32(MCI_POWER_CONTROL_REG
, 0);
417 MicroSecondDelay(100);
420 MCI_TRACE("MciNotifyState(MmcHwInitializationState): TurnOn MCI");
422 // - 0x1D = 29 => should be the clock divider to be less than 400kHz at MCLK = 24Mhz
423 MmioWrite32(MCI_CLOCK_CONTROL_REG
,0x1D | MCI_CLOCK_ENABLE
| MCI_CLOCK_POWERSAVE
);
424 //MmioWrite32(MCI_CLOCK_CONTROL_REG,0x1D | MCI_CLOCK_ENABLE);
427 MmioWrite32(MCI_POWER_CONTROL_REG
,MCI_POWER_OPENDRAIN
| (15<<2));
428 MmioWrite32(MCI_POWER_CONTROL_REG
,MCI_POWER_ROD
| MCI_POWER_OPENDRAIN
| (15<<2) | MCI_POWER_UP
);
429 MicroSecondDelay(10);
430 MmioWrite32(MCI_POWER_CONTROL_REG
,MCI_POWER_ROD
| MCI_POWER_OPENDRAIN
| (15<<2) | MCI_POWER_ON
);
431 MicroSecondDelay(100);
433 // Set Data Length & Data Timer
434 MmioWrite32(MCI_DATA_TIMER_REG
,0xFFFFF);
435 MmioWrite32(MCI_DATA_LENGTH_REG
,8);
437 ASSERT((MmioRead32(MCI_POWER_CONTROL_REG
) & 0x3) == MCI_POWER_ON
);
440 MCI_TRACE("MciNotifyState(MmcIdleState)");
443 MCI_TRACE("MciNotifyState(MmcReadyState)");
445 case MmcIdentificationState
:
446 MCI_TRACE("MciNotifyState(MmcIdentificationState)");
448 case MmcStandByState
:{
449 volatile UINT32 PwrCtrlReg
;
450 MCI_TRACE("MciNotifyState(MmcStandByState)");
452 // Enable MCICMD push-pull drive
453 PwrCtrlReg
= MmioRead32(MCI_POWER_CONTROL_REG
);
454 //Disable Open Drain output
455 PwrCtrlReg
&=~(MCI_POWER_OPENDRAIN
);
456 MmioWrite32(MCI_POWER_CONTROL_REG
,PwrCtrlReg
);
458 // Set MMCI0 clock to 4MHz (24MHz may be possible with cache enabled)
460 // Note: Increasing clock speed causes TX FIFO under-run errors.
461 // So careful when optimising this driver for higher performance.
463 MmioWrite32(MCI_CLOCK_CONTROL_REG
,0x02 | MCI_CLOCK_ENABLE
| MCI_CLOCK_POWERSAVE
);
464 // Set MMCI0 clock to 24MHz (by bypassing the divider)
465 //MmioWrite32(MCI_CLOCK_CONTROL_REG,MCI_CLOCK_BYPASS | MCI_CLOCK_ENABLE);
468 case MmcTransferState
:
469 //MCI_TRACE("MciNotifyState(MmcTransferState)");
471 case MmcSendingDataState
:
472 MCI_TRACE("MciNotifyState(MmcSendingDataState)");
474 case MmcReceiveDataState
:
475 MCI_TRACE("MciNotifyState(MmcReceiveDataState)");
477 case MmcProgrammingState
:
478 MCI_TRACE("MciNotifyState(MmcProgrammingState)");
480 case MmcDisconnectState
:
481 MCI_TRACE("MciNotifyState(MmcDisconnectState)");
489 EFI_GUID mPL180MciDevicePathGuid
= EFI_CALLER_ID_GUID
;
493 IN EFI_DEVICE_PATH_PROTOCOL
**DevicePath
496 EFI_DEVICE_PATH_PROTOCOL
*NewDevicePathNode
;
498 NewDevicePathNode
= CreateDeviceNode(HARDWARE_DEVICE_PATH
,HW_VENDOR_DP
,sizeof(VENDOR_DEVICE_PATH
));
499 CopyGuid(&((VENDOR_DEVICE_PATH
*)NewDevicePathNode
)->Guid
,&mPL180MciDevicePathGuid
);
501 *DevicePath
= NewDevicePathNode
;
505 EFI_MMC_HOST_PROTOCOL gMciHost
= {
517 PL180MciDxeInitialize (
518 IN EFI_HANDLE ImageHandle
,
519 IN EFI_SYSTEM_TABLE
*SystemTable
523 EFI_HANDLE Handle
= NULL
;
525 MCI_TRACE("PL180MciDxeInitialize()");
527 //Publish Component Name, BlockIO protocol interfaces
528 Status
= gBS
->InstallMultipleProtocolInterfaces (
530 &gEfiMmcHostProtocolGuid
, &gMciHost
,
533 ASSERT_EFI_ERROR (Status
);