ArmPlatformPkg/Include/Drivers/PL011Uart.h

   1 /** @file
   2 *
   3 *  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #ifndef __PL011_UART_H__
  16 #define __PL011_UART_H__
  17
  18 #include <Uefi.h>
  19 #include <Protocol/SerialIo.h>
  20
  21 // PL011 Registers
  22 #define UARTDR                    0x000
  23 #define UARTRSR                   0x004
  24 #define UARTECR                   0x004
  25 #define UARTFR                    0x018
  26 #define UARTILPR                  0x020
  27 #define UARTIBRD                  0x024
  28 #define UARTFBRD                  0x028
  29 #define UARTLCR_H                 0x02C
  30 #define UARTCR                    0x030
  31 #define UARTIFLS                  0x034
  32 #define UARTIMSC                  0x038
  33 #define UARTRIS                   0x03C
  34 #define UARTMIS                   0x040
  35 #define UARTICR                   0x044
  36 #define UARTDMACR                 0x048
  37
  38 // Data status bits
  39 #define UART_DATA_ERROR_MASK      0x0F00
  40
  41 // Status reg bits
  42 #define UART_STATUS_ERROR_MASK    0x0F
  43
  44 // Flag reg bits
  45 #define PL011_UARTFR_RI           (1 << 8)  // Ring indicator
  46 #define PL011_UARTFR_TXFE         (1 << 7)  // Transmit FIFO empty
  47 #define PL011_UARTFR_RXFF         (1 << 6)  // Receive  FIFO full
  48 #define PL011_UARTFR_TXFF         (1 << 5)  // Transmit FIFO full
  49 #define PL011_UARTFR_RXFE         (1 << 4)  // Receive  FIFO empty
  50 #define PL011_UARTFR_BUSY         (1 << 3)  // UART busy
  51 #define PL011_UARTFR_DCD          (1 << 2)  // Data carrier detect
  52 #define PL011_UARTFR_DSR          (1 << 1)  // Data set ready
  53 #define PL011_UARTFR_CTS          (1 << 0)  // Clear to send
  54
  55 // Flag reg bits - alternative names
  56 #define UART_TX_EMPTY_FLAG_MASK   PL011_UARTFR_TXFE
  57 #define UART_RX_FULL_FLAG_MASK    PL011_UARTFR_RXFF
  58 #define UART_TX_FULL_FLAG_MASK    PL011_UARTFR_TXFF
  59 #define UART_RX_EMPTY_FLAG_MASK   PL011_UARTFR_RXFE
  60 #define UART_BUSY_FLAG_MASK       PL011_UARTFR_BUSY
  61
  62 // Control reg bits
  63 #define PL011_UARTCR_CTSEN        (1 << 15) // CTS hardware flow control enable
  64 #define PL011_UARTCR_RTSEN        (1 << 14) // RTS hardware flow control enable
  65 #define PL011_UARTCR_RTS          (1 << 11) // Request to send
  66 #define PL011_UARTCR_DTR          (1 << 10) // Data transmit ready.
  67 #define PL011_UARTCR_RXE          (1 << 9)  // Receive enable
  68 #define PL011_UARTCR_TXE          (1 << 8)  // Transmit enable
  69 #define PL011_UARTCR_LBE          (1 << 7)  // Loopback enable
  70 #define PL011_UARTCR_UARTEN       (1 << 0)  // UART Enable
  71
  72 // Line Control Register Bits
  73 #define PL011_UARTLCR_H_SPS       (1 << 7)  // Stick parity select
  74 #define PL011_UARTLCR_H_WLEN_8    (3 << 5)
  75 #define PL011_UARTLCR_H_WLEN_7    (2 << 5)
  76 #define PL011_UARTLCR_H_WLEN_6    (1 << 5)
  77 #define PL011_UARTLCR_H_WLEN_5    (0 << 5)
  78 #define PL011_UARTLCR_H_FEN       (1 << 4)  // FIFOs Enable
  79 #define PL011_UARTLCR_H_STP2      (1 << 3)  // Two stop bits select
  80 #define PL011_UARTLCR_H_EPS       (1 << 2)  // Even parity select
  81 #define PL011_UARTLCR_H_PEN       (1 << 1)  // Parity Enable
  82 #define PL011_UARTLCR_H_BRK       (1 << 0)  // Send break
  83
  84 /*
  85
  86   Programmed hardware of Serial port.
  87
  88   @return    Always return EFI_UNSUPPORTED.
  89
  90 **/
  91 RETURN_STATUS
  92 EFIAPI
  93 PL011UartInitializePort (
  94   IN OUT UINTN               UartBase,
  95   IN OUT UINT64              *BaudRate,
  96   IN OUT UINT32              *ReceiveFifoDepth,
  97   IN OUT EFI_PARITY_TYPE     *Parity,
  98   IN OUT UINT8               *DataBits,
  99   IN OUT EFI_STOP_BITS_TYPE  *StopBits
 100   );
 101
 102 /**
 103   Set the serial device control bits.
 104
 105   @param  UartBase                The base address of the PL011 UART.
 106   @param  Control                 Control bits which are to be set on the serial device.
 107
 108   @retval EFI_SUCCESS             The new control bits were set on the serial device.
 109   @retval EFI_UNSUPPORTED         The serial device does not support this operation.
 110   @retval EFI_DEVICE_ERROR        The serial device is not functioning correctly.
 111
 112 **/
 113 RETURN_STATUS
 114 EFIAPI
 115 PL011UartSetControl (
 116     IN UINTN                    UartBase,
 117     IN UINT32                   Control
 118   );
 119
 120 /**
 121   Get the serial device control bits.
 122
 123   @param  UartBase                The base address of the PL011 UART.
 124   @param  Control                 Control signals read from the serial device.
 125
 126   @retval EFI_SUCCESS             The control bits were read from the serial device.
 127   @retval EFI_DEVICE_ERROR        The serial device is not functioning correctly.
 128
 129 **/
 130 RETURN_STATUS
 131 EFIAPI
 132 PL011UartGetControl (
 133     IN UINTN                    UartBase,
 134     OUT UINT32                  *Control
 135   );
 136
 137 /**
 138   Write data to serial device.
 139
 140   @param  Buffer           Point of data buffer which need to be written.
 141   @param  NumberOfBytes    Number of output bytes which are cached in Buffer.
 142
 143   @retval 0                Write data failed.
 144   @retval !0               Actual number of bytes written to serial device.
 145
 146 **/
 147 UINTN
 148 EFIAPI
 149 PL011UartWrite (
 150   IN  UINTN       UartBase,
 151   IN  UINT8       *Buffer,
 152   IN  UINTN       NumberOfBytes
 153   );
 154
 155 /**
 156   Read data from serial device and save the data in buffer.
 157
 158   @param  Buffer           Point of data buffer which need to be written.
 159   @param  NumberOfBytes    Number of output bytes which are cached in Buffer.
 160
 161   @retval 0                Read data failed.
 162   @retval !0               Actual number of bytes read from serial device.
 163
 164 **/
 165 UINTN
 166 EFIAPI
 167 PL011UartRead (
 168   IN  UINTN       UartBase,
 169   OUT UINT8       *Buffer,
 170   IN  UINTN       NumberOfBytes
 171   );
 172
 173 /**
 174   Check to see if any data is available to be read from the debug device.
 175
 176   @retval EFI_SUCCESS       At least one byte of data is available to be read
 177   @retval EFI_NOT_READY     No data is available to be read
 178   @retval EFI_DEVICE_ERROR  The serial device is not functioning properly
 179
 180 **/
 181 BOOLEAN
 182 EFIAPI
 183 PL011UartPoll (
 184   IN  UINTN       UartBase
 185   );
 186
 187 #endif