ArmPlatformPkg/Include/Drivers/PL011Uart.h

   1 /** @file
   2 *
   3 *  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #ifndef __PL011_UART_H__
  16 #define __PL011_UART_H__
  17
  18 #include <Uefi.h>
  19 #include <Protocol/SerialIo.h>
  20
  21 // PL011 Registers
  22 #define UARTDR                    0x000
  23 #define UARTRSR                   0x004
  24 #define UARTECR                   0x004
  25 #define UARTFR                    0x018
  26 #define UARTILPR                  0x020
  27 #define UARTIBRD                  0x024
  28 #define UARTFBRD                  0x028
  29 #define UARTLCR_H                 0x02C
  30 #define UARTCR                    0x030
  31 #define UARTIFLS                  0x034
  32 #define UARTIMSC                  0x038
  33 #define UARTRIS                   0x03C
  34 #define UARTMIS                   0x040
  35 #define UARTICR                   0x044
  36 #define UARTDMACR                 0x048
  37
  38 // Data status bits
  39 #define UART_DATA_ERROR_MASK      0x0F00
  40
  41 // Status reg bits
  42 #define UART_STATUS_ERROR_MASK    0x0F
  43
  44 // Flag reg bits
  45 #define PL011_UARTFR_RI           (1 << 8)  // Ring indicator
  46 #define PL011_UARTFR_TXFE         (1 << 7)  // Transmit FIFO empty
  47 #define PL011_UARTFR_RXFF         (1 << 6)  // Receive  FIFO full
  48 #define PL011_UARTFR_TXFF         (1 << 5)  // Transmit FIFO full
  49 #define PL011_UARTFR_RXFE         (1 << 4)  // Receive  FIFO empty
  50 #define PL011_UARTFR_BUSY         (1 << 3)  // UART busy
  51 #define PL011_UARTFR_DCD          (1 << 2)  // Data carrier detect
  52 #define PL011_UARTFR_DSR          (1 << 1)  // Data set ready
  53 #define PL011_UARTFR_CTS          (1 << 0)  // Clear to send
  54
  55 // Flag reg bits - alternative names
  56 #define UART_TX_EMPTY_FLAG_MASK   PL011_UARTFR_TXFE
  57 #define UART_RX_FULL_FLAG_MASK    PL011_UARTFR_RXFF
  58 #define UART_TX_FULL_FLAG_MASK    PL011_UARTFR_TXFF
  59 #define UART_RX_EMPTY_FLAG_MASK   PL011_UARTFR_RXFE
  60 #define UART_BUSY_FLAG_MASK       PL011_UARTFR_BUSY
  61
  62 // Control reg bits
  63 #define PL011_UARTCR_CTSEN        (1 << 15) // CTS hardware flow control enable
  64 #define PL011_UARTCR_RTSEN        (1 << 14) // RTS hardware flow control enable
  65 #define PL011_UARTCR_RTS          (1 << 11) // Request to send
  66 #define PL011_UARTCR_DTR          (1 << 10) // Data transmit ready.
  67 #define PL011_UARTCR_RXE          (1 << 9)  // Receive enable
  68 #define PL011_UARTCR_TXE          (1 << 8)  // Transmit enable
  69 #define PL011_UARTCR_LBE          (1 << 7)  // Loopback enable
  70 #define PL011_UARTCR_UARTEN       (1 << 0)  // UART Enable
  71
  72 // Line Control Register Bits
  73 #define PL011_UARTLCR_H_SPS       (1 << 7)  // Stick parity select
  74 #define PL011_UARTLCR_H_WLEN_8    (3 << 5)
  75 #define PL011_UARTLCR_H_WLEN_7    (2 << 5)
  76 #define PL011_UARTLCR_H_WLEN_6    (1 << 5)
  77 #define PL011_UARTLCR_H_WLEN_5    (0 << 5)
  78 #define PL011_UARTLCR_H_FEN       (1 << 4)  // FIFOs Enable
  79 #define PL011_UARTLCR_H_STP2      (1 << 3)  // Two stop bits select
  80 #define PL011_UARTLCR_H_EPS       (1 << 2)  // Even parity select
  81 #define PL011_UARTLCR_H_PEN       (1 << 1)  // Parity Enable
  82 #define PL011_UARTLCR_H_BRK       (1 << 0)  // Send break
  83
  84 /*
  85
  86   Programmed hardware of Serial port.
  87
  88   @return    Always return EFI_UNSUPPORTED.
  89
  90 **/
  91 RETURN_STATUS
  92 EFIAPI
  93 PL011UartInitializePort (
  94   IN OUT UINTN               UartBase,
  95   IN OUT UINT64              *BaudRate,
  96   IN OUT UINT32              *ReceiveFifoDepth,
  97   IN OUT EFI_PARITY_TYPE     *Parity,
  98   IN OUT UINT8               *DataBits,
  99   IN OUT EFI_STOP_BITS_TYPE  *StopBits
 100   );
 101
 102 /**
 103
 104   Assert or deassert the control signals on a serial port.
 105   The following control signals are set according their bit settings :
 106   . Request to Send
 107   . Data Terminal Ready
 108
 109   @param[in]  UartBase  UART registers base address
 110   @param[in]  Control   The following bits are taken into account :
 111                         . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the
 112                           "Request To Send" control signal if this bit is
 113                           equal to one/zero.
 114                         . EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert
 115                           the "Data Terminal Ready" control signal if this
 116                           bit is equal to one/zero.
 117                         . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable
 118                           the hardware loopback if this bit is equal to
 119                           one/zero.
 120                         . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.
 121                         . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/
 122                           disable the hardware flow control based on CTS (Clear
 123                           To Send) and RTS (Ready To Send) control signals.
 124
 125   @retval  RETURN_SUCCESS      The new control bits were set on the serial device.
 126   @retval  RETURN_UNSUPPORTED  The serial device does not support this operation.
 127
 128 **/
 129 RETURN_STATUS
 130 EFIAPI
 131 PL011UartSetControl (
 132   IN UINTN   UartBase,
 133   IN UINT32  Control
 134   );
 135
 136 /**
 137
 138   Retrieve the status of the control bits on a serial device.
 139
 140   @param[in]   UartBase  UART registers base address
 141   @param[out]  Control   Status of the control bits on a serial device :
 142
 143                          . EFI_SERIAL_DATA_CLEAR_TO_SEND, EFI_SERIAL_DATA_SET_READY,
 144                            EFI_SERIAL_RING_INDICATE, EFI_SERIAL_CARRIER_DETECT,
 145                            EFI_SERIAL_REQUEST_TO_SEND, EFI_SERIAL_DATA_TERMINAL_READY
 146                            are all related to the DTE (Data Terminal Equipment) and
 147                            DCE (Data Communication Equipment) modes of operation of
 148                            the serial device.
 149                          . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the receive
 150                            buffer is empty, 0 otherwise.
 151                          . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the transmit
 152                            buffer is empty, 0 otherwise.
 153                          . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if the
 154                            hardware loopback is enabled (the ouput feeds the receive
 155                            buffer), 0 otherwise.
 156                          . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one if a
 157                            loopback is accomplished by software, 0 otherwise.
 158                          . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to one if the
 159                            hardware flow control based on CTS (Clear To Send) and RTS
 160                            (Ready To Send) control signals is enabled, 0 otherwise.
 161
 162
 163   @retval RETURN_SUCCESS  The control bits were read from the serial device.
 164
 165 **/
 166 RETURN_STATUS
 167 EFIAPI
 168 PL011UartGetControl (
 169   IN UINTN     UartBase,
 170   OUT UINT32  *Control
 171   );
 172
 173 /**
 174   Write data to serial device.
 175
 176   @param  Buffer           Point of data buffer which need to be written.
 177   @param  NumberOfBytes    Number of output bytes which are cached in Buffer.
 178
 179   @retval 0                Write data failed.
 180   @retval !0               Actual number of bytes written to serial device.
 181
 182 **/
 183 UINTN
 184 EFIAPI
 185 PL011UartWrite (
 186   IN  UINTN       UartBase,
 187   IN  UINT8       *Buffer,
 188   IN  UINTN       NumberOfBytes
 189   );
 190
 191 /**
 192   Read data from serial device and save the data in buffer.
 193
 194   @param  Buffer           Point of data buffer which need to be written.
 195   @param  NumberOfBytes    Number of output bytes which are cached in Buffer.
 196
 197   @retval 0                Read data failed.
 198   @retval !0               Actual number of bytes read from serial device.
 199
 200 **/
 201 UINTN
 202 EFIAPI
 203 PL011UartRead (
 204   IN  UINTN       UartBase,
 205   OUT UINT8       *Buffer,
 206   IN  UINTN       NumberOfBytes
 207   );
 208
 209 /**
 210   Check to see if any data is available to be read from the debug device.
 211
 212   @retval EFI_SUCCESS       At least one byte of data is available to be read
 213   @retval EFI_NOT_READY     No data is available to be read
 214   @retval EFI_DEVICE_ERROR  The serial device is not functioning properly
 215
 216 **/
 217 BOOLEAN
 218 EFIAPI
 219 PL011UartPoll (
 220   IN  UINTN       UartBase
 221   );
 222
 223 #endif