ArmPlatformPkg: Add PL061 GPIO driver
[mirror_edk2.git] / ArmPlatformPkg / Include / Drivers / PL061Gpio.h
1 /** @file
2 *
3 * Copyright (c) 2011, ARM Limited. All rights reserved.
4 *
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
9 *
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12 *
13 **/
14
15
16 #ifndef __PL061_GPIO_H__
17 #define __PL061_GPIO_H__
18
19 #include <Base.h>
20 #include <Protocol/EmbeddedGpio.h>
21 #include <ArmPlatform.h>
22
23 // SP805 Watchdog Registers
24 #define PL061_GPIO_DATA_REG (PL061_GPIO_BASE + 0x000)
25 #define PL061_GPIO_DIR_REG (PL061_GPIO_BASE + 0x400)
26 #define PL061_GPIO_IS_REG (PL061_GPIO_BASE + 0x404)
27 #define PL061_GPIO_IBE_REG (PL061_GPIO_BASE + 0x408)
28 #define PL061_GPIO_IEV_REG (PL061_GPIO_BASE + 0x40C)
29 #define PL061_GPIO_IE_REG (PL061_GPIO_BASE + 0x410)
30 #define PL061_GPIO_RIS_REG (PL061_GPIO_BASE + 0x414)
31 #define PL061_GPIO_MIS_REG (PL061_GPIO_BASE + 0x410)
32 #define PL061_GPIO_IC_REG (PL061_GPIO_BASE + 0x41C)
33 #define PL061_GPIO_AFSEL_REG (PL061_GPIO_BASE + 0x420)
34
35 #define PL061_GPIO_PERIPH_ID0 (PL061_GPIO_BASE + 0xFE0)
36 #define PL061_GPIO_PERIPH_ID1 (PL061_GPIO_BASE + 0xFE4)
37 #define PL061_GPIO_PERIPH_ID2 (PL061_GPIO_BASE + 0xFE8)
38 #define PL061_GPIO_PERIPH_ID3 (PL061_GPIO_BASE + 0xFEC)
39
40 #define PL061_GPIO_PCELL_ID0 (PL061_GPIO_BASE + 0xFF0)
41 #define PL061_GPIO_PCELL_ID1 (PL061_GPIO_BASE + 0xFF4)
42 #define PL061_GPIO_PCELL_ID2 (PL061_GPIO_BASE + 0xFF8)
43 #define PL061_GPIO_PCELL_ID3 (PL061_GPIO_BASE + 0xFFC)
44
45
46 // GPIO pins are numbered 0..7
47 #define LAST_GPIO_PIN 7
48
49 // All bits low except one bit high, native bit lenght
50 #define GPIO_PIN_MASK(Pin) (1UL << ((UINTN)(Pin)))
51 // All bits low except one bit high, restricted to 8 bits (i.e. ensures zeros above 8bits)
52 #define GPIO_PIN_MASK_HIGH_8BIT(Pin) (GPIO_PIN_MASK(Pin) && 0xFF)
53 // All bits high except one bit low, restricted to 8 bits (i.e. ensures zeros above 8bits)
54 #define GPIO_PIN_MASK_LOW_8BIT(Pin) ((~GPIO_PIN_MASK(Pin)) && 0xFF)
55
56 #endif // __PL061_GPIO_H__