ArmPlatformPkg/Include/Drivers/PL111Lcd.h

   1 /** @file  PL111Lcd.h
   2
   3  Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
   4  This program and the accompanying materials
   5  are licensed and made available under the terms and conditions of the BSD License
   6  which accompanies this distribution.  The full text of the license may be found at
   7  http://opensource.org/licenses/bsd-license.php
   8
   9  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11
  12  **/
  13
  14 #ifndef _PL111LCD_H__
  15 #define _PL111LCD_H__
  16
  17 #include <ArmPlatform.h>
  18
  19 /**********************************************************************
  20  *
  21  *  This header file contains all the bits of the PL111 that are
  22  *  platform independent.
  23  *
  24  **********************************************************************/
  25
  26 // Controller Register Offsets
  27 #define PL111_REG_LCD_TIMING_0            (PL111_CLCD_BASE + 0x000)
  28 #define PL111_REG_LCD_TIMING_1            (PL111_CLCD_BASE + 0x004)
  29 #define PL111_REG_LCD_TIMING_2            (PL111_CLCD_BASE + 0x008)
  30 #define PL111_REG_LCD_TIMING_3            (PL111_CLCD_BASE + 0x00C)
  31 #define PL111_REG_LCD_UP_BASE             (PL111_CLCD_BASE + 0x010)
  32 #define PL111_REG_LCD_LP_BASE             (PL111_CLCD_BASE + 0x014)
  33 #define PL111_REG_LCD_CONTROL             (PL111_CLCD_BASE + 0x018)
  34 #define PL111_REG_LCD_IMSC                (PL111_CLCD_BASE + 0x01C)
  35 #define PL111_REG_LCD_RIS                 (PL111_CLCD_BASE + 0x020)
  36 #define PL111_REG_LCD_MIS                 (PL111_CLCD_BASE + 0x024)
  37 #define PL111_REG_LCD_ICR                 (PL111_CLCD_BASE + 0x028)
  38 #define PL111_REG_LCD_UP_CURR             (PL111_CLCD_BASE + 0x02C)
  39 #define PL111_REG_LCD_LP_CURR             (PL111_CLCD_BASE + 0x030)
  40 #define PL111_REG_LCD_PALETTE             (PL111_CLCD_BASE + 0x200)
  41
  42 // Identification Register Offsets
  43 #define PL111_REG_CLCD_PERIPH_ID_0        (PL111_CLCD_BASE + 0xFE0)
  44 #define PL111_REG_CLCD_PERIPH_ID_1        (PL111_CLCD_BASE + 0xFE4)
  45 #define PL111_REG_CLCD_PERIPH_ID_2        (PL111_CLCD_BASE + 0xFE8)
  46 #define PL111_REG_CLCD_PERIPH_ID_3        (PL111_CLCD_BASE + 0xFEC)
  47 #define PL111_REG_CLCD_P_CELL_ID_0        (PL111_CLCD_BASE + 0xFF0)
  48 #define PL111_REG_CLCD_P_CELL_ID_1        (PL111_CLCD_BASE + 0xFF4)
  49 #define PL111_REG_CLCD_P_CELL_ID_2        (PL111_CLCD_BASE + 0xFF8)
  50 #define PL111_REG_CLCD_P_CELL_ID_3        (PL111_CLCD_BASE + 0xFFC)
  51
  52 /**********************************************************************/
  53
  54 // Register components (register bits)
  55
  56 // This should make life easier to program specific settings in the different registers
  57 // by simplifying the setting up of the individual bits of each register
  58 // and then assembling the final register value.
  59
  60 /**********************************************************************/
  61
  62 // Register: PL111_REG_LCD_TIMING_0
  63 #define HOR_AXIS_PANEL(hbp,hfp,hsw,hor_res) (UINT32)(((UINT32)(hbp) << 24) | ((UINT32)(hfp) << 16) | ((UINT32)(hsw) << 8) | (((UINT32)((hor_res)/16)-1) << 2))
  64
  65 // Register: PL111_REG_LCD_TIMING_1
  66 #define VER_AXIS_PANEL(vbp,vfp,vsw,ver_res) (UINT32)(((UINT32)(vbp) << 24) | ((UINT32)(vfp) << 16) | ((UINT32)(vsw) << 10) | ((ver_res)-1))
  67
  68 // Register: PL111_REG_LCD_TIMING_2
  69 #define PL111_BIT_SHIFT_PCD_HI            27
  70 #define PL111_BIT_SHIFT_BCD               26
  71 #define PL111_BIT_SHIFT_CPL               16
  72 #define PL111_BIT_SHIFT_IOE               14
  73 #define PL111_BIT_SHIFT_IPC               13
  74 #define PL111_BIT_SHIFT_IHS               12
  75 #define PL111_BIT_SHIFT_IVS               11
  76 #define PL111_BIT_SHIFT_ACB               6
  77 #define PL111_BIT_SHIFT_CLKSEL            5
  78 #define PL111_BIT_SHIFT_PCD_LO            0
  79
  80 #define PL111_BCD                         (1 << 26)
  81 #define PL111_IPC                         (1 << 13)
  82 #define PL111_IHS                         (1 << 12)
  83 #define PL111_IVS                         (1 << 11)
  84
  85 #define CLK_SIG_POLARITY(hor_res)         (UINT32)(PL111_BCD | PL111_IPC | PL111_IHS | PL111_IVS | (((hor_res)-1) << 16))
  86
  87 // Register: PL111_REG_LCD_TIMING_3
  88 #define PL111_BIT_SHIFT_LEE               16
  89 #define PL111_BIT_SHIFT_LED               0
  90
  91 #define PL111_CTRL_WATERMARK              (1 << 16)
  92 #define PL111_CTRL_LCD_V_COMP             (1 << 12)
  93 #define PL111_CTRL_LCD_PWR                (1 << 11)
  94 #define PL111_CTRL_BEPO                   (1 << 10)
  95 #define PL111_CTRL_BEBO                   (1 << 9)
  96 #define PL111_CTRL_BGR                    (1 << 8)
  97 #define PL111_CTRL_LCD_DUAL               (1 << 7)
  98 #define PL111_CTRL_LCD_MONO_8             (1 << 6)
  99 #define PL111_CTRL_LCD_TFT                (1 << 5)
 100 #define PL111_CTRL_LCD_BW                 (1 << 4)
 101 #define PL111_CTRL_LCD_1BPP               (0 << 1)
 102 #define PL111_CTRL_LCD_2BPP               (1 << 1)
 103 #define PL111_CTRL_LCD_4BPP               (2 << 1)
 104 #define PL111_CTRL_LCD_8BPP               (3 << 1)
 105 #define PL111_CTRL_LCD_16BPP              (4 << 1)
 106 #define PL111_CTRL_LCD_24BPP              (5 << 1)
 107 #define PL111_CTRL_LCD_16BPP_565          (6 << 1)
 108 #define PL111_CTRL_LCD_12BPP_444          (7 << 1)
 109 #define PL111_CTRL_LCD_BPP(Bpp)           ((Bpp) << 1)
 110 #define PL111_CTRL_LCD_EN                 1
 111
 112 /**********************************************************************/
 113
 114 // Register: PL111_REG_LCD_TIMING_0
 115 #define PL111_LCD_TIMING_0_HBP(hbp)       (((hbp) & 0xFF) << 24)
 116 #define PL111_LCD_TIMING_0_HFP(hfp)       (((hfp) & 0xFF) << 16)
 117 #define PL111_LCD_TIMING_0_HSW(hsw)       (((hsw) & 0xFF) << 8)
 118 #define PL111_LCD_TIMING_0_PPL(ppl)       (((hsw) & 0x3F) << 2)
 119
 120 // Register: PL111_REG_LCD_TIMING_1
 121 #define PL111_LCD_TIMING_1_VBP(vbp)       (((vbp) & 0xFF) << 24)
 122 #define PL111_LCD_TIMING_1_VFP(vfp)       (((vfp) & 0xFF) << 16)
 123 #define PL111_LCD_TIMING_1_VSW(vsw)       (((vsw) & 0x3F) << 10)
 124 #define PL111_LCD_TIMING_1_LPP(lpp)        ((lpp) & 0xFC)
 125
 126 // Register: PL111_REG_LCD_TIMING_2
 127 #define PL111_BIT_MASK_PCD_HI             0xF8000000
 128 #define PL111_BIT_MASK_BCD                0x04000000
 129 #define PL111_BIT_MASK_CPL                0x03FF0000
 130 #define PL111_BIT_MASK_IOE                0x00004000
 131 #define PL111_BIT_MASK_IPC                0x00002000
 132 #define PL111_BIT_MASK_IHS                0x00001000
 133 #define PL111_BIT_MASK_IVS                0x00000800
 134 #define PL111_BIT_MASK_ACB                0x000007C0
 135 #define PL111_BIT_MASK_CLKSEL             0x00000020
 136 #define PL111_BIT_MASK_PCD_LO             0x0000001F
 137
 138 // Register: PL111_REG_LCD_TIMING_3
 139 #define PL111_BIT_MASK_LEE                0x00010000
 140 #define PL111_BIT_MASK_LED                0x0000007F
 141
 142 #endif /* _PL111LCD_H__ */