ArmPlatformPkg/Include/Drivers/PL310L2Cache.h

   1 /** @file
   2 *
   3 *  Copyright (c) 2011, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #ifndef L2CACHELIB_H_
  16 #define L2CACHELIB_H_
  17
  18 #define L2X0_CACHEID            0x000
  19 #define L2X0_CTRL               0x100
  20 #define L2X0_AUXCTRL            0x104
  21 #define L230_TAG_LATENCY        0x108
  22 #define L230_DATA_LATENCY       0x10C
  23 #define L2X0_INTCLEAR           0x220
  24 #define L2X0_CACHE_SYNC         0x730
  25 #define L2X0_INVWAY             0x77C
  26 #define L2X0_CLEAN_WAY          0x7BC
  27 #define L2X0_PFCTRL             0xF60
  28 #define L2X0_PWRCTRL            0xF80
  29
  30 #define L2X0_CACHEID_IMPLEMENTER_ARM        0x41
  31 #define L2X0_CACHEID_PARTNUM_PL310          0x03
  32
  33 #define L2X0_CTRL_ENABLED                   0x1
  34 #define L2X0_CTRL_DISABLED                  0x0
  35
  36 #define L2X0_AUXCTRL_EXCLUSIVE              (1 << 12)
  37 #define L2X0_AUXCTRL_ASSOCIATIVITY          (1 << 16)
  38 #define L2X0_AUXCTRL_WAYSIZE_MASK           (3 << 17)
  39 #define L2X0_AUXCTRL_WAYSIZE_16KB           (1 << 17)
  40 #define L2X0_AUXCTRL_WAYSIZE_32KB           (2 << 17)
  41 #define L2X0_AUXCTRL_WAYSIZE_64KB           (3 << 17)
  42 #define L2X0_AUXCTRL_WAYSIZE_128KB          (4 << 17)
  43 #define L2X0_AUXCTRL_WAYSIZE_256KB          (5 << 17)
  44 #define L2X0_AUXCTRL_WAYSIZE_512KB          (6 << 17)
  45 #define L2X0_AUXCTRL_EM                     (1 << 20)
  46 #define L2X0_AUXCTRL_SHARED_OVERRIDE        (1 << 22)
  47 #define L2x0_AUXCTRL_AW_AWCACHE             (0 << 23)
  48 #define L2x0_AUXCTRL_AW_NOALLOC             (1 << 23)
  49 #define L2x0_AUXCTRL_AW_OVERRIDE            (2 << 23)
  50 #define L2X0_AUXCTRL_SBO                    (1 << 25)
  51 #define L2X0_AUXCTRL_NSAC                   (1 << 27)
  52 #define L2x0_AUXCTRL_DPREFETCH              (1 << 28)
  53 #define L2x0_AUXCTRL_IPREFETCH              (1 << 29)
  54 #define L2x0_AUXCTRL_EARLY_BRESP            (1 << 30)
  55
  56 #define L2x0_LATENCY_1_CYCLE                 0
  57 #define L2x0_LATENCY_2_CYCLES                1
  58 #define L2x0_LATENCY_3_CYCLES                2
  59 #define L2x0_LATENCY_4_CYCLES                3
  60 #define L2x0_LATENCY_5_CYCLES                4
  61 #define L2x0_LATENCY_6_CYCLES                5
  62 #define L2x0_LATENCY_7_CYCLES                6
  63 #define L2x0_LATENCY_8_CYCLES                7
  64
  65 #define PL310_LATENCIES(Write,Read,Setup)      (((Write) << 8) | ((Read) << 4) | (Setup))
  66 #define PL310_TAG_LATENCIES(Write,Read,Setup)  PL310_LATENCIES(Write,Read,Setup)
  67 #define PL310_DATA_LATENCIES(Write,Read,Setup) PL310_LATENCIES(Write,Read,Setup)
  68
  69 VOID
  70 L2x0CacheInit (
  71   IN  UINTN   L2x0Base,
  72   IN  UINT32  L2x0TagLatencies,
  73   IN  UINT32  L2x0DataLatencies,
  74   IN  UINT32  L2x0AuxValue,
  75   IN  UINT32  L2x0AuxMask,
  76   IN  BOOLEAN CacheEnabled
  77   );
  78
  79 #endif /* L2CACHELIB_H_ */