3 * Copyright (c) 2011-2014, ARM Limited. All rights reserved.
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 #include <Library/ArmLib.h>
18 #include <Library/ArmGicLib.h>
19 #include <Library/ArmPlatformLib.h>
20 #include <Library/ArmPlatformSecLib.h>
21 #include <Library/DebugLib.h>
22 #include <Library/PcdLib.h>
23 #include <Library/PrintLib.h>
24 #include <Library/SerialPortLib.h>
26 // When the firmware is built as not Standalone, the secondary cores need to wait the firmware
27 // entirely written into DRAM. It is the firmware from DRAM which will wake up the secondary cores.
29 NonSecureWaitForFirmware (
33 VOID (*SecondaryStart
)(VOID
);
34 UINTN AcknowledgeInterrupt
;
37 // The secondary cores will execute the firmware once wake from WFI.
38 SecondaryStart
= (VOID (*)())PcdGet32 (PcdFvBaseAddress
);
42 // Acknowledge the interrupt and send End of Interrupt signal.
43 AcknowledgeInterrupt
= ArmGicAcknowledgeInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase
), &InterruptId
);
44 // Check if it is a valid interrupt ID
45 if (InterruptId
< ArmGicGetMaxNumInterrupts (PcdGet32 (PcdGicDistributorBase
))) {
46 // Got a valid SGI number hence signal End of Interrupt
47 ArmGicEndOfInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase
), AcknowledgeInterrupt
);
50 // Jump to secondary core entry point.
53 // PEI Core should always load and never return
58 Call before jumping to Normal World
60 This function allows the firmware platform to do extra actions before
61 jumping to the Normal World
65 ArmPlatformSecExtraAction (
67 OUT UINTN
* JumpAddress
73 if (FeaturePcdGet (PcdStandalone
) == FALSE
) {
76 // Warning: This code assumes the DRAM has already been initialized by ArmPlatformSecLib
79 if (ArmPlatformIsPrimaryCore (MpId
)) {
80 UINTN
* StartAddress
= (UINTN
*)PcdGet32(PcdFvBaseAddress
);
82 // Patch the DRAM to make an infinite loop at the start address
83 *StartAddress
= 0xEAFFFFFE; // opcode for while(1)
85 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"Waiting for firmware at 0x%08X ...\n\r",StartAddress
);
86 SerialPortWrite ((UINT8
*) Buffer
, CharCount
);
88 *JumpAddress
= PcdGet32(PcdFvBaseAddress
);
90 // When the primary core is stopped by the hardware debugger to copy the firmware
91 // into DRAM. The secondary cores are still running. As soon as the first bytes of
92 // the firmware are written into DRAM, the secondary cores will start to execute the
93 // code even if the firmware is not entirely written into the memory.
94 // That's why the secondary cores need to be parked in WFI and wake up once the
97 *JumpAddress
= (UINTN
)NonSecureWaitForFirmware
;
99 } else if (FeaturePcdGet (PcdSystemMemoryInitializeInSec
)) {
102 // Warning: This code assumes the DRAM has already been initialized by ArmPlatformSecLib
105 if (ArmPlatformIsPrimaryCore (MpId
)) {
106 // Signal the secondary cores they can jump to PEI phase
107 ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase
), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE
, 0x0E, PcdGet32 (PcdGicSgiIntId
));
109 // To enter into Non Secure state, we need to make a return from exception
110 *JumpAddress
= PcdGet32(PcdFvBaseAddress
);
112 // We wait for the primary core to finish to initialize the System Memory. Otherwise the secondary
113 // cores would make crash the system by setting their stacks in DRAM before the primary core has not
114 // finished to initialize the system memory.
115 *JumpAddress
= (UINTN
)NonSecureWaitForFirmware
;
118 *JumpAddress
= PcdGet32(PcdFvBaseAddress
);