ArmPlatformPkg/Library/PL011UartLib/PL011Uart.h

   1 /** @file
   2 *
   3 *  Copyright (c) 2011-2016, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #ifndef __PL011_UART_H__
  16 #define __PL011_UART_H__
  17
  18 #define PL011_VARIANT_ZTE 1
  19
  20 // PL011 Registers
  21 #if FixedPcdGet8 (PL011UartRegOffsetVariant) == PL011_VARIANT_ZTE
  22 #define UARTDR                    0x004
  23 #define UARTRSR                   0x010
  24 #define UARTECR                   0x010
  25 #define UARTFR                    0x014
  26 #define UARTIBRD                  0x024
  27 #define UARTFBRD                  0x028
  28 #define UARTLCR_H                 0x030
  29 #define UARTCR                    0x034
  30 #define UARTIFLS                  0x038
  31 #define UARTIMSC                  0x040
  32 #define UARTRIS                   0x044
  33 #define UARTMIS                   0x048
  34 #define UARTICR                   0x04c
  35 #define UARTDMACR                 0x050
  36 #else
  37 #define UARTDR                    0x000
  38 #define UARTRSR                   0x004
  39 #define UARTECR                   0x004
  40 #define UARTFR                    0x018
  41 #define UARTILPR                  0x020
  42 #define UARTIBRD                  0x024
  43 #define UARTFBRD                  0x028
  44 #define UARTLCR_H                 0x02C
  45 #define UARTCR                    0x030
  46 #define UARTIFLS                  0x034
  47 #define UARTIMSC                  0x038
  48 #define UARTRIS                   0x03C
  49 #define UARTMIS                   0x040
  50 #define UARTICR                   0x044
  51 #define UARTDMACR                 0x048
  52 #endif
  53
  54 #define UARTPID0                  0xFE0
  55 #define UARTPID1                  0xFE4
  56 #define UARTPID2                  0xFE8
  57 #define UARTPID3                  0xFEC
  58
  59 // Data status bits
  60 #define UART_DATA_ERROR_MASK      0x0F00
  61
  62 // Status reg bits
  63 #define UART_STATUS_ERROR_MASK    0x0F
  64
  65 // Flag reg bits
  66 #if FixedPcdGet8 (PL011UartRegOffsetVariant) == PL011_VARIANT_ZTE
  67 #define PL011_UARTFR_RI           (1 << 0)  // Ring indicator
  68 #define PL011_UARTFR_TXFE         (1 << 7)  // Transmit FIFO empty
  69 #define PL011_UARTFR_RXFF         (1 << 6)  // Receive  FIFO full
  70 #define PL011_UARTFR_TXFF         (1 << 5)  // Transmit FIFO full
  71 #define PL011_UARTFR_RXFE         (1 << 4)  // Receive  FIFO empty
  72 #define PL011_UARTFR_BUSY         (1 << 8)  // UART busy
  73 #define PL011_UARTFR_DCD          (1 << 2)  // Data carrier detect
  74 #define PL011_UARTFR_DSR          (1 << 3)  // Data set ready
  75 #define PL011_UARTFR_CTS          (1 << 1)  // Clear to send
  76 #else
  77 #define PL011_UARTFR_RI           (1 << 8)  // Ring indicator
  78 #define PL011_UARTFR_TXFE         (1 << 7)  // Transmit FIFO empty
  79 #define PL011_UARTFR_RXFF         (1 << 6)  // Receive  FIFO full
  80 #define PL011_UARTFR_TXFF         (1 << 5)  // Transmit FIFO full
  81 #define PL011_UARTFR_RXFE         (1 << 4)  // Receive  FIFO empty
  82 #define PL011_UARTFR_BUSY         (1 << 3)  // UART busy
  83 #define PL011_UARTFR_DCD          (1 << 2)  // Data carrier detect
  84 #define PL011_UARTFR_DSR          (1 << 1)  // Data set ready
  85 #define PL011_UARTFR_CTS          (1 << 0)  // Clear to send
  86 #endif
  87
  88 // Flag reg bits - alternative names
  89 #define UART_TX_EMPTY_FLAG_MASK   PL011_UARTFR_TXFE
  90 #define UART_RX_FULL_FLAG_MASK    PL011_UARTFR_RXFF
  91 #define UART_TX_FULL_FLAG_MASK    PL011_UARTFR_TXFF
  92 #define UART_RX_EMPTY_FLAG_MASK   PL011_UARTFR_RXFE
  93 #define UART_BUSY_FLAG_MASK       PL011_UARTFR_BUSY
  94
  95 // Control reg bits
  96 #define PL011_UARTCR_CTSEN        (1 << 15) // CTS hardware flow control enable
  97 #define PL011_UARTCR_RTSEN        (1 << 14) // RTS hardware flow control enable
  98 #define PL011_UARTCR_RTS          (1 << 11) // Request to send
  99 #define PL011_UARTCR_DTR          (1 << 10) // Data transmit ready.
 100 #define PL011_UARTCR_RXE          (1 << 9)  // Receive enable
 101 #define PL011_UARTCR_TXE          (1 << 8)  // Transmit enable
 102 #define PL011_UARTCR_LBE          (1 << 7)  // Loopback enable
 103 #define PL011_UARTCR_UARTEN       (1 << 0)  // UART Enable
 104
 105 // Line Control Register Bits
 106 #define PL011_UARTLCR_H_SPS       (1 << 7)  // Stick parity select
 107 #define PL011_UARTLCR_H_WLEN_8    (3 << 5)
 108 #define PL011_UARTLCR_H_WLEN_7    (2 << 5)
 109 #define PL011_UARTLCR_H_WLEN_6    (1 << 5)
 110 #define PL011_UARTLCR_H_WLEN_5    (0 << 5)
 111 #define PL011_UARTLCR_H_FEN       (1 << 4)  // FIFOs Enable
 112 #define PL011_UARTLCR_H_STP2      (1 << 3)  // Two stop bits select
 113 #define PL011_UARTLCR_H_EPS       (1 << 2)  // Even parity select
 114 #define PL011_UARTLCR_H_PEN       (1 << 1)  // Parity Enable
 115 #define PL011_UARTLCR_H_BRK       (1 << 0)  // Send break
 116
 117 #define PL011_UARTPID2_VER(X)     (((X) >> 4) & 0xF)
 118 #define PL011_VER_R1P4            0x2
 119
 120 #endif