3 * Copyright (c) 2011, ARM Limited. All rights reserved.
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include <Library/ArmGicLib.h>
16 #include <Library/ArmMPCoreMailBoxLib.h>
17 #include <Chipset/ArmV7.h>
19 #include "PrePeiCore.h"
22 * This is the main function for secondary cores. They loop around until a non Null value is written to
23 * SYS_FLAGS register.The SYS_FLAGS register is platform specific.
24 * Note:The secondary cores, while executing secondary_main, assumes that:
25 * : SGI 0 is configured as Non-secure interrupt
26 * : Priority Mask is configured to allow SGI 0
27 * : Interrupt Distributor and CPU interfaces are enabled
36 // Function pointer to Secondary Core entry point
37 VOID (*secondary_start
)(VOID
);
38 UINTN secondary_entry_addr
=0;
40 // Clear Secondary cores MailBox
41 ArmClearMPCoreMailbox();
43 while (secondary_entry_addr
= ArmGetMPCoreMailbox(), secondary_entry_addr
== 0) {
45 // Acknowledge the interrupt and send End of Interrupt signal.
46 ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase
), PRIMARY_CORE_ID
);
49 secondary_start
= (VOID (*)())secondary_entry_addr
;
51 // Jump to secondary core entry point.
54 // The secondaries shouldn't reach here
61 IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
64 EFI_SEC_PEI_HAND_OFF SecCoreData
;
66 EFI_PEI_PPI_DESCRIPTOR
*PpiList
;
67 UINTN TemporaryRamBase
;
68 UINTN TemporaryRamSize
;
70 CreatePpiList (&PpiListSize
, &PpiList
);
72 // Enable the GIC Distributor
73 ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase
));
75 // If ArmVe has not been built as Standalone then we need to wake up the secondary cores
76 if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores
)) {
77 // Sending SGI to all the Secondary CPU interfaces
78 ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase
), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE
, 0x0E);
81 // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at
82 // the base of the primary core stack
83 PpiListSize
= ALIGN_VALUE(PpiListSize
, 0x4);
84 TemporaryRamBase
= (UINTN
)PcdGet32 (PcdCPUCoresStackBase
) + PpiListSize
;
85 TemporaryRamSize
= (UINTN
)PcdGet32 (PcdCPUCorePrimaryStackSize
) - PpiListSize
;
88 // Bind this information into the SEC hand-off state
89 // Note: this must be in sync with the stuff in the asm file
90 // Note also: HOBs (pei temp ram) MUST be above stack
92 SecCoreData
.DataSize
= sizeof(EFI_SEC_PEI_HAND_OFF
);
93 SecCoreData
.BootFirmwareVolumeBase
= (VOID
*)(UINTN
)PcdGet32 (PcdFvBaseAddress
);
94 SecCoreData
.BootFirmwareVolumeSize
= PcdGet32 (PcdFvSize
);
95 SecCoreData
.TemporaryRamBase
= (VOID
*)TemporaryRamBase
; // We run on the primary core (and so we use the first stack)
96 SecCoreData
.TemporaryRamSize
= TemporaryRamSize
;
97 SecCoreData
.PeiTemporaryRamBase
= SecCoreData
.TemporaryRamBase
;
98 SecCoreData
.PeiTemporaryRamSize
= SecCoreData
.TemporaryRamSize
/ 2;
99 SecCoreData
.StackBase
= (VOID
*)((UINTN
)(SecCoreData
.TemporaryRamBase
) + (SecCoreData
.TemporaryRamSize
/2));
100 SecCoreData
.StackSize
= SecCoreData
.TemporaryRamSize
/ 2;
102 // Jump to PEI core entry point
103 (PeiCoreEntryPoint
)(&SecCoreData
, PpiList
);