ArmPlatformPkg/PrePeiCore/MainMPCore.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2011, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #include <Library/DebugLib.h>
  16 #include <Library/PcdLib.h>
  17 #include <Library/ArmMPCoreMailBoxLib.h>
  18 #include <Chipset/ArmV7.h>
  19 #include <Drivers/PL390Gic.h>
  20
  21 #include "PrePeiCore.h"
  22
  23 extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable;
  24
  25 /*
  26  * This is the main function for secondary cores. They loop around until a non Null value is written to
  27  * SYS_FLAGS register.The SYS_FLAGS register is platform specific.
  28  * Note:The secondary cores, while executing secondary_main, assumes that:
  29  *      : SGI 0 is configured as Non-secure interrupt
  30  *      : Priority Mask is configured to allow SGI 0
  31  *      : Interrupt Distributor and CPU interfaces are enabled
  32  *
  33  */
  34 VOID
  35 EFIAPI
  36 SecondaryMain (
  37   IN UINTN CoreId
  38   )
  39 {
  40   // Function pointer to Secondary Core entry point
  41   VOID (*secondary_start)(VOID);
  42   UINTN secondary_entry_addr=0;
  43
  44   // Clear Secondary cores MailBox
  45   ArmClearMPCoreMailbox();
  46
  47   while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {
  48     ArmCallWFI();
  49     // Acknowledge the interrupt and send End of Interrupt signal.
  50     PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);
  51   }
  52
  53   secondary_start = (VOID (*)())secondary_entry_addr;
  54
  55   // Jump to secondary core entry point.
  56   secondary_start();
  57
  58   // The secondaries shouldn't reach here
  59   ASSERT(FALSE);
  60 }
  61
  62 VOID
  63 EFIAPI
  64 PrimaryMain (
  65   IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint
  66   )
  67 {
  68   EFI_SEC_PEI_HAND_OFF        SecCoreData;
  69
  70   //Enable the GIC Distributor
  71   PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));
  72
  73   // If ArmVe has not been built as Standalone then we need to wake up the secondary cores
  74   if (FeaturePcdGet(PcdStandalone) == FALSE) {
  75     // Sending SGI to all the Secondary CPU interfaces
  76     PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
  77   }
  78
  79   //
  80   // Bind this information into the SEC hand-off state
  81   // Note: this must be in sync with the stuff in the asm file
  82   // Note also:  HOBs (pei temp ram) MUST be above stack
  83   //
  84   SecCoreData.DataSize               = sizeof(EFI_SEC_PEI_HAND_OFF);
  85   SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress);
  86   SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize);
  87   SecCoreData.TemporaryRamBase       = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)
  88   SecCoreData.TemporaryRamSize       = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);
  89   SecCoreData.PeiTemporaryRamBase    = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));
  90   SecCoreData.PeiTemporaryRamSize    = SecCoreData.TemporaryRamSize / 2;
  91   SecCoreData.StackBase              = SecCoreData.TemporaryRamBase;
  92   SecCoreData.StackSize              = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;
  93
  94   // Jump to PEI core entry point
  95   (PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable);
  96 }