58eeef1c3a7e5a6e1023a4541d41e977c814b756
[mirror_edk2.git] / ArmPlatformPkg / PrePeiCore / MainMPCore.c
1 /** @file
2 *
3 * Copyright (c) 2011, ARM Limited. All rights reserved.
4 *
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
9 *
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12 *
13 **/
14
15 #include <Library/ArmGicLib.h>
16 #include <Library/ArmMPCoreMailBoxLib.h>
17 #include <Chipset/ArmV7.h>
18
19 #include "PrePeiCore.h"
20
21 /*
22 * This is the main function for secondary cores. They loop around until a non Null value is written to
23 * SYS_FLAGS register.The SYS_FLAGS register is platform specific.
24 * Note:The secondary cores, while executing secondary_main, assumes that:
25 * : SGI 0 is configured as Non-secure interrupt
26 * : Priority Mask is configured to allow SGI 0
27 * : Interrupt Distributor and CPU interfaces are enabled
28 *
29 */
30 VOID
31 EFIAPI
32 SecondaryMain (
33 IN UINTN MpId
34 )
35 {
36 // Function pointer to Secondary Core entry point
37 VOID (*secondary_start)(VOID);
38 UINTN secondary_entry_addr=0;
39
40 // Clear Secondary cores MailBox
41 ArmClearMPCoreMailbox();
42
43 while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {
44 ArmCallWFI();
45 // Acknowledge the interrupt and send End of Interrupt signal.
46 ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);
47 }
48
49 secondary_start = (VOID (*)())secondary_entry_addr;
50
51 // Jump to secondary core entry point.
52 secondary_start();
53
54 // The secondaries shouldn't reach here
55 ASSERT(FALSE);
56 }
57
58 VOID
59 EFIAPI
60 PrimaryMain (
61 IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
62 )
63 {
64 EFI_SEC_PEI_HAND_OFF SecCoreData;
65
66 // Enable the GIC Distributor
67 ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));
68
69 // If ArmVe has not been built as Standalone then we need to wake up the secondary cores
70 if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {
71 // Sending SGI to all the Secondary CPU interfaces
72 ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
73 }
74
75 //
76 // Bind this information into the SEC hand-off state
77 // Note: this must be in sync with the stuff in the asm file
78 // Note also: HOBs (pei temp ram) MUST be above stack
79 //
80 SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);
81 SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdFvBaseAddress);
82 SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);
83 SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize); // We consider we run on the primary core (and so we use the first stack)
84 SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize);
85 SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));
86 SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2;
87 SecCoreData.StackBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize/2));
88 SecCoreData.StackSize = SecCoreData.TemporaryRamSize / 2;
89
90 // Jump to PEI core entry point
91 (PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable);
92 }