ArmPlatformPkg/PrePeiCore/MainMPCore.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2011, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #include <Library/ArmGicLib.h>
  16
  17 #include <Ppi/ArmMpCoreInfo.h>
  18
  19 #include <Chipset/ArmV7.h>
  20
  21 #include "PrePeiCore.h"
  22
  23 /*
  24  * This is the main function for secondary cores. They loop around until a non Null value is written to
  25  * SYS_FLAGS register.The SYS_FLAGS register is platform specific.
  26  * Note:The secondary cores, while executing secondary_main, assumes that:
  27  *      : SGI 0 is configured as Non-secure interrupt
  28  *      : Priority Mask is configured to allow SGI 0
  29  *      : Interrupt Distributor and CPU interfaces are enabled
  30  *
  31  */
  32 VOID
  33 EFIAPI
  34 SecondaryMain (
  35   IN UINTN MpId
  36   )
  37 {
  38   EFI_STATUS              Status;
  39   UINTN                   PpiListSize;
  40   UINTN                   PpiListCount;
  41   EFI_PEI_PPI_DESCRIPTOR  *PpiList;
  42   ARM_MP_CORE_INFO_PPI    *ArmMpCoreInfoPpi;
  43   UINTN                   Index;
  44   UINTN                   ArmCoreCount;
  45   ARM_CORE_INFO           *ArmCoreInfoTable;
  46   UINT32                  ClusterId;
  47   UINT32                  CoreId;
  48   VOID                    (*SecondaryStart)(VOID);
  49   UINTN                   SecondaryEntryAddr;
  50
  51   ClusterId = GET_CLUSTER_ID(MpId);
  52   CoreId    = GET_CORE_ID(MpId);
  53
  54   // Get the gArmMpCoreInfoPpiGuid
  55   PpiListSize = 0;
  56   ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);
  57   PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);
  58   for (Index = 0; Index < PpiListCount; Index++, PpiList++) {
  59     if (CompareGuid (PpiList->Guid, &gArmMpCoreInfoPpiGuid) == TRUE) {
  60       break;
  61     }
  62   }
  63
  64   // On MP Core Platform we must implement the ARM MP Core Info PPI
  65   ASSERT (Index != PpiListCount);
  66
  67   ArmMpCoreInfoPpi = PpiList->Ppi;
  68   ArmCoreCount = 0;
  69   Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
  70   ASSERT_EFI_ERROR (Status);
  71
  72   // Find the core in the ArmCoreTable
  73   for (Index = 0; Index < ArmCoreCount; Index++) {
  74     if ((ArmCoreInfoTable[Index].ClusterId == ClusterId) && (ArmCoreInfoTable[Index].CoreId == CoreId)) {
  75       break;
  76     }
  77   }
  78
  79   // The ARM Core Info Table must define every core
  80   ASSERT (Index != ArmCoreCount);
  81
  82   // Clear Secondary cores MailBox
  83   MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);
  84
  85   SecondaryEntryAddr = 0;
  86   while (SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress), SecondaryEntryAddr == 0) {
  87     ArmCallWFI ();
  88     // Acknowledge the interrupt and send End of Interrupt signal.
  89     ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);
  90   }
  91
  92   // Jump to secondary core entry point.
  93   SecondaryStart = (VOID (*)())SecondaryEntryAddr;
  94   SecondaryStart();
  95
  96   // The secondaries shouldn't reach here
  97   ASSERT(FALSE);
  98 }
  99
 100 VOID
 101 EFIAPI
 102 PrimaryMain (
 103   IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint
 104   )
 105 {
 106   EFI_SEC_PEI_HAND_OFF        SecCoreData;
 107   UINTN                       PpiListSize;
 108   EFI_PEI_PPI_DESCRIPTOR      *PpiList;
 109   UINTN                       TemporaryRamBase;
 110   UINTN                       TemporaryRamSize;
 111
 112   CreatePpiList (&PpiListSize, &PpiList);
 113
 114   // Enable the GIC Distributor
 115   ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));
 116
 117   // If ArmVe has not been built as Standalone then we need to wake up the secondary cores
 118   if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {
 119     // Sending SGI to all the Secondary CPU interfaces
 120     ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
 121   }
 122
 123   // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at
 124   // the base of the primary core stack
 125   PpiListSize = ALIGN_VALUE(PpiListSize, 0x4);
 126   TemporaryRamBase = (UINTN)PcdGet32 (PcdCPUCoresStackBase) + PpiListSize;
 127   TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;
 128
 129   //
 130   // Bind this information into the SEC hand-off state
 131   // Note: this must be in sync with the stuff in the asm file
 132   // Note also:  HOBs (pei temp ram) MUST be above stack
 133   //
 134   SecCoreData.DataSize               = sizeof(EFI_SEC_PEI_HAND_OFF);
 135   SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdFvBaseAddress);
 136   SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);
 137   SecCoreData.TemporaryRamBase       = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)
 138   SecCoreData.TemporaryRamSize       = TemporaryRamSize;
 139   SecCoreData.PeiTemporaryRamBase    = SecCoreData.TemporaryRamBase;
 140   SecCoreData.PeiTemporaryRamSize    = SecCoreData.TemporaryRamSize / 2;
 141   SecCoreData.StackBase              = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize/2));
 142   SecCoreData.StackSize              = SecCoreData.TemporaryRamSize / 2;
 143
 144   // Jump to PEI core entry point
 145   (PeiCoreEntryPoint)(&SecCoreData, PpiList);
 146 }