ArmPlatformPkg/PrePeiCore/MainMPCore.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2011, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #include <PiPei.h>
  16 #include <Library/DebugLib.h>
  17 #include <Library/PcdLib.h>
  18 #include <Library/ArmMPCoreMailBoxLib.h>
  19 #include <Chipset/ArmV7.h>
  20 #include <Drivers/PL390Gic.h>
  21
  22 extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable;
  23
  24 /*
  25  * This is the main function for secondary cores. They loop around until a non Null value is written to
  26  * SYS_FLAGS register.The SYS_FLAGS register is platform specific.
  27  * Note:The secondary cores, while executing secondary_main, assumes that:
  28  *      : SGI 0 is configured as Non-secure interrupt
  29  *      : Priority Mask is configured to allow SGI 0
  30  *      : Interrupt Distributor and CPU interfaces are enabled
  31  *
  32  */
  33 VOID
  34 EFIAPI
  35 secondary_main(IN UINTN CoreId)
  36 {
  37         //Function pointer to Secondary Core entry point
  38         VOID (*secondary_start)(VOID);
  39         UINTN secondary_entry_addr=0;
  40
  41         //Clear Secondary cores MailBox
  42         ArmClearMPCoreMailbox();
  43
  44         while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {
  45                 ArmCallWFI();
  46           //Acknowledge the interrupt and send End of Interrupt signal.
  47                 PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);
  48         }
  49
  50         secondary_start = (VOID (*)())secondary_entry_addr;
  51
  52         //Jump to secondary core entry point.
  53         secondary_start();
  54
  55         //the secondaries shouldn't reach here
  56         ASSERT(FALSE);
  57 }
  58
  59 VOID primary_main (
  60   IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint
  61   )
  62 {
  63         EFI_SEC_PEI_HAND_OFF        SecCoreData;
  64
  65         //Enable the GIC Distributor
  66         PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));
  67
  68         // If ArmVe has not been built as Standalone then we need to wake up the secondary cores
  69         if (FeaturePcdGet(PcdStandalone) == FALSE) {
  70                 // Sending SGI to all the Secondary CPU interfaces
  71                 PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
  72         }
  73
  74         //
  75         // Bind this information into the SEC hand-off state
  76         // Note: this must be in sync with the stuff in the asm file
  77         // Note also:  HOBs (pei temp ram) MUST be above stack
  78         //
  79         SecCoreData.DataSize               = sizeof(EFI_SEC_PEI_HAND_OFF);
  80         SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdEmbeddedFdBaseAddress);
  81         SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdEmbeddedFdSize);
  82         SecCoreData.TemporaryRamBase       = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)
  83         SecCoreData.TemporaryRamSize       = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);
  84         SecCoreData.PeiTemporaryRamBase    = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));
  85         SecCoreData.PeiTemporaryRamSize    = SecCoreData.TemporaryRamSize / 2;
  86         SecCoreData.StackBase              = SecCoreData.TemporaryRamBase;
  87         SecCoreData.StackSize              = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;
  88
  89         // jump to pei core entry point
  90         (PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable);
  91 }