ArmPlatformPkg/PrePeiCore/MainMPCore.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #include <Library/ArmGicLib.h>
  16
  17 #include <Ppi/ArmMpCoreInfo.h>
  18
  19 #include "PrePeiCore.h"
  20
  21 /*
  22  * This is the main function for secondary cores. They loop around until a non Null value is written to
  23  * SYS_FLAGS register.The SYS_FLAGS register is platform specific.
  24  * Note:The secondary cores, while executing secondary_main, assumes that:
  25  *      : SGI 0 is configured as Non-secure interrupt
  26  *      : Priority Mask is configured to allow SGI 0
  27  *      : Interrupt Distributor and CPU interfaces are enabled
  28  *
  29  */
  30 VOID
  31 EFIAPI
  32 SecondaryMain (
  33   IN UINTN MpId
  34   )
  35 {
  36   EFI_STATUS              Status;
  37   UINTN                   PpiListSize;
  38   UINTN                   PpiListCount;
  39   EFI_PEI_PPI_DESCRIPTOR  *PpiList;
  40   ARM_MP_CORE_INFO_PPI    *ArmMpCoreInfoPpi;
  41   UINTN                   Index;
  42   UINTN                   ArmCoreCount;
  43   ARM_CORE_INFO           *ArmCoreInfoTable;
  44   UINT32                  ClusterId;
  45   UINT32                  CoreId;
  46   VOID                    (*SecondaryStart)(VOID);
  47   UINTN                   SecondaryEntryAddr;
  48
  49   ClusterId = GET_CLUSTER_ID(MpId);
  50   CoreId    = GET_CORE_ID(MpId);
  51
  52   // Get the gArmMpCoreInfoPpiGuid
  53   PpiListSize = 0;
  54   ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);
  55   PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);
  56   for (Index = 0; Index < PpiListCount; Index++, PpiList++) {
  57     if (CompareGuid (PpiList->Guid, &gArmMpCoreInfoPpiGuid) == TRUE) {
  58       break;
  59     }
  60   }
  61
  62   // On MP Core Platform we must implement the ARM MP Core Info PPI
  63   ASSERT (Index != PpiListCount);
  64
  65   ArmMpCoreInfoPpi = PpiList->Ppi;
  66   ArmCoreCount = 0;
  67   Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
  68   ASSERT_EFI_ERROR (Status);
  69
  70   // Find the core in the ArmCoreTable
  71   for (Index = 0; Index < ArmCoreCount; Index++) {
  72     if ((ArmCoreInfoTable[Index].ClusterId == ClusterId) && (ArmCoreInfoTable[Index].CoreId == CoreId)) {
  73       break;
  74     }
  75   }
  76
  77   // The ARM Core Info Table must define every core
  78   ASSERT (Index != ArmCoreCount);
  79
  80   // Clear Secondary cores MailBox
  81   MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);
  82
  83   SecondaryEntryAddr = 0;
  84   while (SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress), SecondaryEntryAddr == 0) {
  85     ArmCallWFI ();
  86     // Acknowledge the interrupt and send End of Interrupt signal.
  87     ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);
  88   }
  89
  90   // Jump to secondary core entry point.
  91   SecondaryStart = (VOID (*)())SecondaryEntryAddr;
  92   SecondaryStart();
  93
  94   // The secondaries shouldn't reach here
  95   ASSERT(FALSE);
  96 }
  97
  98 VOID
  99 EFIAPI
 100 PrimaryMain (
 101   IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint
 102   )
 103 {
 104   EFI_SEC_PEI_HAND_OFF        SecCoreData;
 105   UINTN                       PpiListSize;
 106   EFI_PEI_PPI_DESCRIPTOR      *PpiList;
 107   UINTN                       TemporaryRamBase;
 108   UINTN                       TemporaryRamSize;
 109
 110   CreatePpiList (&PpiListSize, &PpiList);
 111
 112   // Enable the GIC Distributor
 113   ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));
 114
 115   // If ArmVe has not been built as Standalone then we need to wake up the secondary cores
 116   if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {
 117     // Sending SGI to all the Secondary CPU interfaces
 118     ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));
 119   }
 120
 121   // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at
 122   // the base of the primary core stack
 123   PpiListSize = ALIGN_VALUE(PpiListSize, 0x4);
 124   TemporaryRamBase = (UINTN)PcdGet32 (PcdCPUCoresStackBase) + PpiListSize;
 125   TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;
 126
 127   // Make sure the size is 8-byte aligned. Once divided by 2, the size should be 4-byte aligned
 128   // to ensure the stack pointer is 4-byte aligned.
 129   TemporaryRamSize = TemporaryRamSize - (TemporaryRamSize & (0x8-1));
 130
 131   //
 132   // Bind this information into the SEC hand-off state
 133   // Note: this must be in sync with the stuff in the asm file
 134   // Note also:  HOBs (pei temp ram) MUST be above stack
 135   //
 136   SecCoreData.DataSize               = sizeof(EFI_SEC_PEI_HAND_OFF);
 137   SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdFvBaseAddress);
 138   SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);
 139   SecCoreData.TemporaryRamBase       = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)
 140   SecCoreData.TemporaryRamSize       = TemporaryRamSize;
 141   SecCoreData.PeiTemporaryRamBase    = SecCoreData.TemporaryRamBase;
 142   SecCoreData.PeiTemporaryRamSize    = SecCoreData.TemporaryRamSize / 2;
 143   SecCoreData.StackBase              = (VOID *)ALIGN_VALUE((UINTN)(SecCoreData.TemporaryRamBase) + SecCoreData.PeiTemporaryRamSize, 0x4);
 144   SecCoreData.StackSize              = (TemporaryRamBase + TemporaryRamSize) - (UINTN)SecCoreData.StackBase;
 145
 146   // Jump to PEI core entry point
 147   (PeiCoreEntryPoint)(&SecCoreData, PpiList);
 148 }