ArmPlatformPkg/PrePeiCore/MainMPCore.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2011, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #include <Library/ArmMPCoreMailBoxLib.h>
  16 #include <Chipset/ArmV7.h>
  17 #include <Drivers/PL390Gic.h>
  18
  19 #include "PrePeiCore.h"
  20
  21 extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable;
  22
  23 /*
  24  * This is the main function for secondary cores. They loop around until a non Null value is written to
  25  * SYS_FLAGS register.The SYS_FLAGS register is platform specific.
  26  * Note:The secondary cores, while executing secondary_main, assumes that:
  27  *      : SGI 0 is configured as Non-secure interrupt
  28  *      : Priority Mask is configured to allow SGI 0
  29  *      : Interrupt Distributor and CPU interfaces are enabled
  30  *
  31  */
  32 VOID
  33 EFIAPI
  34 SecondaryMain (
  35   IN UINTN CoreId
  36   )
  37 {
  38   // Function pointer to Secondary Core entry point
  39   VOID (*secondary_start)(VOID);
  40   UINTN secondary_entry_addr=0;
  41
  42   // Clear Secondary cores MailBox
  43   ArmClearMPCoreMailbox();
  44
  45   while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {
  46     ArmCallWFI();
  47     // Acknowledge the interrupt and send End of Interrupt signal.
  48     PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);
  49   }
  50
  51   secondary_start = (VOID (*)())secondary_entry_addr;
  52
  53   // Jump to secondary core entry point.
  54   secondary_start();
  55
  56   // The secondaries shouldn't reach here
  57   ASSERT(FALSE);
  58 }
  59
  60 VOID
  61 EFIAPI
  62 PrimaryMain (
  63   IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint
  64   )
  65 {
  66   EFI_SEC_PEI_HAND_OFF        SecCoreData;
  67
  68   //Enable the GIC Distributor
  69   PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));
  70
  71   // If ArmVe has not been built as Standalone then we need to wake up the secondary cores
  72   if (!PcdGet32(PcdStandalone)) {
  73     // Sending SGI to all the Secondary CPU interfaces
  74     PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
  75   }
  76
  77   //
  78   // Bind this information into the SEC hand-off state
  79   // Note: this must be in sync with the stuff in the asm file
  80   // Note also:  HOBs (pei temp ram) MUST be above stack
  81   //
  82   SecCoreData.DataSize               = sizeof(EFI_SEC_PEI_HAND_OFF);
  83   SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress);
  84   SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize);
  85   SecCoreData.TemporaryRamBase       = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)
  86   SecCoreData.TemporaryRamSize       = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);
  87   SecCoreData.PeiTemporaryRamBase    = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));
  88   SecCoreData.PeiTemporaryRamSize    = SecCoreData.TemporaryRamSize / 2;
  89   SecCoreData.StackBase              = SecCoreData.TemporaryRamBase;
  90   SecCoreData.StackSize              = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;
  91
  92   // Jump to PEI core entry point
  93   (PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable);
  94 }