ArmPlatformPkg/PrePeiCore/MainMPCore.c

   1 /** @file
   2
   3   Copyright (c) 2011-2014, ARM Limited. All rights reserved.
   4
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7 **/
   8
   9 #include <Library/ArmGicLib.h>
  10
  11 #include <Ppi/ArmMpCoreInfo.h>
  12
  13 #include "PrePeiCore.h"
  14
  15 /*
  16  * This is the main function for secondary cores. They loop around until a non Null value is written to
  17  * SYS_FLAGS register.The SYS_FLAGS register is platform specific.
  18  * Note:The secondary cores, while executing secondary_main, assumes that:
  19  *      : SGI 0 is configured as Non-secure interrupt
  20  *      : Priority Mask is configured to allow SGI 0
  21  *      : Interrupt Distributor and CPU interfaces are enabled
  22  *
  23  */
  24 VOID
  25 EFIAPI
  26 SecondaryMain (
  27   IN UINTN  MpId
  28   )
  29 {
  30   EFI_STATUS              Status;
  31   UINTN                   PpiListSize;
  32   UINTN                   PpiListCount;
  33   EFI_PEI_PPI_DESCRIPTOR  *PpiList;
  34   ARM_MP_CORE_INFO_PPI    *ArmMpCoreInfoPpi;
  35   UINTN                   Index;
  36   UINTN                   ArmCoreCount;
  37   ARM_CORE_INFO           *ArmCoreInfoTable;
  38   UINT32                  ClusterId;
  39   UINT32                  CoreId;
  40
  41   VOID  (*SecondaryStart)(
  42     VOID
  43     );
  44   UINTN  SecondaryEntryAddr;
  45   UINTN  AcknowledgeInterrupt;
  46   UINTN  InterruptId;
  47
  48   ClusterId = GET_CLUSTER_ID (MpId);
  49   CoreId    = GET_CORE_ID (MpId);
  50
  51   // Get the gArmMpCoreInfoPpiGuid
  52   PpiListSize = 0;
  53   ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);
  54   PpiListCount = PpiListSize / sizeof (EFI_PEI_PPI_DESCRIPTOR);
  55   for (Index = 0; Index < PpiListCount; Index++, PpiList++) {
  56     if (CompareGuid (PpiList->Guid, &gArmMpCoreInfoPpiGuid) == TRUE) {
  57       break;
  58     }
  59   }
  60
  61   // On MP Core Platform we must implement the ARM MP Core Info PPI
  62   ASSERT (Index != PpiListCount);
  63
  64   ArmMpCoreInfoPpi = PpiList->Ppi;
  65   ArmCoreCount     = 0;
  66   Status           = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
  67   ASSERT_EFI_ERROR (Status);
  68
  69   // Find the core in the ArmCoreTable
  70   for (Index = 0; Index < ArmCoreCount; Index++) {
  71     if ((GET_MPIDR_AFF1 (ArmCoreInfoTable[Index].Mpidr) == ClusterId) &&
  72         (GET_MPIDR_AFF0 (ArmCoreInfoTable[Index].Mpidr) == CoreId))
  73     {
  74       break;
  75     }
  76   }
  77
  78   // The ARM Core Info Table must define every core
  79   ASSERT (Index != ArmCoreCount);
  80
  81   // Clear Secondary cores MailBox
  82   MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);
  83
  84   do {
  85     ArmCallWFI ();
  86
  87     // Read the Mailbox
  88     SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);
  89
  90     // Acknowledge the interrupt and send End of Interrupt signal.
  91     AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), &InterruptId);
  92     // Check if it is a valid interrupt ID
  93     if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet64 (PcdGicDistributorBase))) {
  94       // Got a valid SGI number hence signal End of Interrupt
  95       ArmGicEndOfInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);
  96     }
  97   } while (SecondaryEntryAddr == 0);
  98
  99   // Jump to secondary core entry point.
 100   SecondaryStart = (VOID (*)()) SecondaryEntryAddr;
 101   SecondaryStart ();
 102
 103   // The secondaries shouldn't reach here
 104   ASSERT (FALSE);
 105 }
 106
 107 VOID
 108 EFIAPI
 109 PrimaryMain (
 110   IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint
 111   )
 112 {
 113   EFI_SEC_PEI_HAND_OFF    SecCoreData;
 114   UINTN                   PpiListSize;
 115   EFI_PEI_PPI_DESCRIPTOR  *PpiList;
 116   UINTN                   TemporaryRamBase;
 117   UINTN                   TemporaryRamSize;
 118
 119   CreatePpiList (&PpiListSize, &PpiList);
 120
 121   // Enable the GIC Distributor
 122   ArmGicEnableDistributor (PcdGet64 (PcdGicDistributorBase));
 123
 124   // If ArmVe has not been built as Standalone then we need to wake up the secondary cores
 125   if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {
 126     // Sending SGI to all the Secondary CPU interfaces
 127     ArmGicSendSgiTo (PcdGet64 (PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));
 128   }
 129
 130   // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at
 131   // the base of the primary core stack
 132   PpiListSize      = ALIGN_VALUE (PpiListSize, CPU_STACK_ALIGNMENT);
 133   TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;
 134   TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;
 135
 136   //
 137   // Bind this information into the SEC hand-off state
 138   // Note: this must be in sync with the stuff in the asm file
 139   // Note also:  HOBs (pei temp ram) MUST be above stack
 140   //
 141   SecCoreData.DataSize               = sizeof (EFI_SEC_PEI_HAND_OFF);
 142   SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress);
 143   SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);
 144   SecCoreData.TemporaryRamBase       = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)
 145   SecCoreData.TemporaryRamSize       = TemporaryRamSize;
 146   SecCoreData.PeiTemporaryRamBase    = SecCoreData.TemporaryRamBase;
 147   SecCoreData.PeiTemporaryRamSize    = ALIGN_VALUE (SecCoreData.TemporaryRamSize / 2, CPU_STACK_ALIGNMENT);
 148   SecCoreData.StackBase              = (VOID *)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize);
 149   SecCoreData.StackSize              = (TemporaryRamBase + TemporaryRamSize) - (UINTN)SecCoreData.StackBase;
 150
 151   // Jump to PEI core entry point
 152   PeiCoreEntryPoint (&SecCoreData, PpiList);
 153 }