9f7de371f48c51abd55f92d9e038f10e0c30fccb
[mirror_edk2.git] / ArmPlatformPkg / PrePeiCore / MainUniCore.c
1 /** @file
2 *
3 * Copyright (c) 2011, ARM Limited. All rights reserved.
4 *
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
9 *
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12 *
13 **/
14
15 #include <Chipset/ArmV7.h>
16
17 #include "PrePeiCore.h"
18
19 VOID
20 EFIAPI
21 SecondaryMain (
22 IN UINTN MpId
23 )
24 {
25 ASSERT(FALSE);
26 }
27
28 VOID
29 EFIAPI
30 PrimaryMain (
31 IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
32 )
33 {
34 EFI_SEC_PEI_HAND_OFF SecCoreData;
35
36
37 //
38 // Bind this information into the SEC hand-off state
39 // Note: this must be in sync with the stuff in the asm file
40 // Note also: HOBs (pei temp ram) MUST be above stack
41 //
42 SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);
43 SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdFvBaseAddress);
44 SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);
45 SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize); // We consider we run on the primary core (and so we use the first stack)
46 SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize);
47 SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));
48 SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2;
49 SecCoreData.StackBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize/2));
50 SecCoreData.StackSize = SecCoreData.TemporaryRamSize / 2;
51
52 // jump to pei core entry point
53 (PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable);
54 }