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1 /** @file
2 *
3 * Copyright (c) 2011, ARM Limited. All rights reserved.
4 *
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
9 *
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12 *
13 **/
14
15 #include <Library/DebugLib.h>
16 #include <Library/PcdLib.h>
17 #include <Chipset/ArmV7.h>
18
19 #include "PrePeiCore.h"
20
21 extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable;
22
23 VOID
24 EFIAPI
25 SecondaryMain (
26 IN UINTN CoreId
27 )
28 {
29 ASSERT(FALSE);
30 }
31
32 VOID
33 EFIAPI
34 PrimaryMain (
35 IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
36 )
37 {
38 EFI_SEC_PEI_HAND_OFF SecCoreData;
39
40
41 //
42 // Bind this information into the SEC hand-off state
43 // Note: this must be in sync with the stuff in the asm file
44 // Note also: HOBs (pei temp ram) MUST be above stack
45 //
46 SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);
47 SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress);
48 SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize);
49 SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)
50 SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);
51 SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));
52 SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2;
53 SecCoreData.StackBase = SecCoreData.TemporaryRamBase;
54 SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;
55
56 // jump to pei core entry point
57 (PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable);
58 }