ArmPlatformPkg/PrePeiCore/PrePeiCore.c

   1 /** @file
   2 *  Main file supporting the transition to PEI Core in Normal World for Versatile Express
   3 *
   4 *  Copyright (c) 2011, ARM Limited. All rights reserved.
   5 *
   6 *  This program and the accompanying materials
   7 *  are licensed and made available under the terms and conditions of the BSD License
   8 *  which accompanies this distribution.  The full text of the license may be found at
   9 *  http://opensource.org/licenses/bsd-license.php
  10 *
  11 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 *
  14 **/
  15
  16 #include <PiPei.h>
  17 #include <Ppi/TemporaryRamSupport.h>
  18 #include <Library/DebugLib.h>
  19 #include <Library/PcdLib.h>
  20 #include <Library/IoLib.h>
  21 #include <Library/BaseLib.h>
  22 #include <Library/BaseMemoryLib.h>
  23 #include <Library/ArmLib.h>
  24 #include <Chipset/ArmV7.h>
  25
  26 EFI_STATUS
  27 EFIAPI
  28 SecTemporaryRamSupport (
  29   IN CONST EFI_PEI_SERVICES   **PeiServices,
  30   IN EFI_PHYSICAL_ADDRESS     TemporaryMemoryBase,
  31   IN EFI_PHYSICAL_ADDRESS     PermanentMemoryBase,
  32   IN UINTN                    CopySize
  33   );
  34
  35 VOID
  36 SecSwitchStack (
  37   INTN    StackDelta
  38   );
  39
  40 TEMPORARY_RAM_SUPPORT_PPI   mSecTemporaryRamSupportPpi = {SecTemporaryRamSupport};
  41
  42 EFI_PEI_PPI_DESCRIPTOR      gSecPpiTable[] = {
  43   {
  44     EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  45     &gEfiTemporaryRamSupportPpiGuid,
  46     &mSecTemporaryRamSupportPpi
  47   }
  48 };
  49
  50 // Vector Table for Pei Phase
  51 VOID  PeiVectorTable (VOID);
  52
  53
  54 VOID
  55 CEntryPoint (
  56   IN  UINTN                     CoreId,
  57   IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint
  58   )
  59 {
  60   //Clean Data cache
  61   ArmCleanInvalidateDataCache();
  62
  63   //Invalidate instruction cache
  64   ArmInvalidateInstructionCache();
  65
  66   // Enable Instruction & Data caches
  67   ArmEnableDataCache();
  68   ArmEnableInstructionCache();
  69
  70   //
  71   // Note: Doesn't have to Enable CPU interface in non-secure world,
  72   // as Non-secure interface is already enabled in Secure world.
  73   //
  74
  75   // Write VBAR - The Vector table must be 32-byte aligned
  76   ASSERT(((UINT32)PeiVectorTable & ((1 << 5)-1)) == 0);
  77   ArmWriteVBar((UINT32)PeiVectorTable);
  78
  79   //Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.
  80
  81   //If not primary Jump to Secondary Main
  82   if(0 == CoreId) {
  83     //Goto primary Main.
  84     primary_main(PeiCoreEntryPoint);
  85   } else {
  86     secondary_main(CoreId);
  87   }
  88
  89   // PEI Core should always load and never return
  90   ASSERT (FALSE);
  91 }
  92
  93 EFI_STATUS
  94 EFIAPI
  95 SecTemporaryRamSupport (
  96   IN CONST EFI_PEI_SERVICES   **PeiServices,
  97   IN EFI_PHYSICAL_ADDRESS     TemporaryMemoryBase,
  98   IN EFI_PHYSICAL_ADDRESS     PermanentMemoryBase,
  99   IN UINTN                    CopySize
 100   )
 101 {
 102   //
 103   // Migrate the whole temporary memory to permenent memory.
 104   //
 105   CopyMem (
 106     (VOID*)(UINTN)PermanentMemoryBase,
 107     (VOID*)(UINTN)TemporaryMemoryBase,
 108     CopySize
 109     );
 110
 111   SecSwitchStack((UINTN)(PermanentMemoryBase - TemporaryMemoryBase));
 112
 113   return EFI_SUCCESS;
 114 }
 115
 116 VOID PeiCommonExceptionEntry(UINT32 Entry, UINT32 LR) {
 117   switch (Entry) {
 118   case 0:
 119     DEBUG((EFI_D_ERROR,"Reset Exception at 0x%X\n",LR));
 120     break;
 121   case 1:
 122     DEBUG((EFI_D_ERROR,"Undefined Exception at 0x%X\n",LR));
 123     break;
 124   case 2:
 125     DEBUG((EFI_D_ERROR,"SWI Exception at 0x%X\n",LR));
 126     break;
 127   case 3:
 128     DEBUG((EFI_D_ERROR,"PrefetchAbort Exception at 0x%X\n",LR));
 129     break;
 130   case 4:
 131     DEBUG((EFI_D_ERROR,"DataAbort Exception at 0x%X\n",LR));
 132     break;
 133   case 5:
 134     DEBUG((EFI_D_ERROR,"Reserved Exception at 0x%X\n",LR));
 135     break;
 136   case 6:
 137     DEBUG((EFI_D_ERROR,"IRQ Exception at 0x%X\n",LR));
 138     break;
 139   case 7:
 140     DEBUG((EFI_D_ERROR,"FIQ Exception at 0x%X\n",LR));
 141     break;
 142   default:
 143     DEBUG((EFI_D_ERROR,"Unknown Exception at 0x%X\n",LR));
 144     break;
 145   }
 146   while(1);
 147 }