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1 /** @file
2 * Main file supporting the transition to PEI Core in Normal World for Versatile Express
3 *
4 * Copyright (c) 2011, ARM Limited. All rights reserved.
5 *
6 * This program and the accompanying materials
7 * are licensed and made available under the terms and conditions of the BSD License
8 * which accompanies this distribution. The full text of the license may be found at
9 * http://opensource.org/licenses/bsd-license.php
10 *
11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 *
14 **/
15
16 #include <Library/DebugLib.h>
17 #include <Library/PcdLib.h>
18 #include <Library/IoLib.h>
19 #include <Library/BaseLib.h>
20 #include <Library/BaseMemoryLib.h>
21 #include <Library/PrintLib.h>
22 #include <Library/ArmLib.h>
23 #include <Library/SerialPortLib.h>
24 #include <Chipset/ArmV7.h>
25
26 #include "PrePeiCore.h"
27
28 EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mSecTemporaryRamSupportPpi = {SecTemporaryRamSupport};
29
30 EFI_PEI_PPI_DESCRIPTOR gSecPpiTable[] = {
31 {
32 EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
33 &gEfiTemporaryRamSupportPpiGuid,
34 &mSecTemporaryRamSupportPpi
35 }
36 };
37
38 VOID
39 CEntryPoint (
40 IN UINTN CoreId,
41 IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
42 )
43 {
44 //Clean Data cache
45 ArmCleanInvalidateDataCache();
46
47 //Invalidate instruction cache
48 ArmInvalidateInstructionCache();
49
50 // Enable Instruction & Data caches
51 ArmEnableDataCache ();
52 ArmEnableInstructionCache ();
53
54 //
55 // Note: Doesn't have to Enable CPU interface in non-secure world,
56 // as Non-secure interface is already enabled in Secure world.
57 //
58
59 // Write VBAR - The Vector table must be 32-byte aligned
60 ASSERT(((UINT32)PeiVectorTable & ((1 << 5)-1)) == 0);
61 ArmWriteVBar((UINT32)PeiVectorTable);
62
63 //Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.
64
65 //If not primary Jump to Secondary Main
66 if(0 == CoreId) {
67 //Goto primary Main.
68 PrimaryMain (PeiCoreEntryPoint);
69 } else {
70 SecondaryMain (CoreId);
71 }
72
73 // PEI Core should always load and never return
74 ASSERT (FALSE);
75 }
76
77 EFI_STATUS
78 EFIAPI
79 SecTemporaryRamSupport (
80 IN CONST EFI_PEI_SERVICES **PeiServices,
81 IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
82 IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
83 IN UINTN CopySize
84 )
85 {
86 //
87 // Migrate the whole temporary memory to permenent memory.
88 //
89 CopyMem (
90 (VOID*)(UINTN)PermanentMemoryBase,
91 (VOID*)(UINTN)TemporaryMemoryBase,
92 CopySize
93 );
94
95 SecSwitchStack((UINTN)(PermanentMemoryBase - TemporaryMemoryBase));
96
97 return EFI_SUCCESS;
98 }
99
100 VOID
101 PeiCommonExceptionEntry (
102 IN UINT32 Entry,
103 IN UINT32 LR
104 )
105 {
106 CHAR8 Buffer[100];
107 UINTN CharCount;
108
109 switch (Entry) {
110 case 0:
111 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reset Exception at 0x%X\n\r",LR);
112 break;
113 case 1:
114 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Undefined Exception at 0x%X\n\r",LR);
115 break;
116 case 2:
117 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"SWI Exception at 0x%X\n\r",LR);
118 break;
119 case 3:
120 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"PrefetchAbort Exception at 0x%X\n\r",LR);
121 break;
122 case 4:
123 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"DataAbort Exception at 0x%X\n\r",LR);
124 break;
125 case 5:
126 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reserved Exception at 0x%X\n\r",LR);
127 break;
128 case 6:
129 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"IRQ Exception at 0x%X\n\r",LR);
130 break;
131 case 7:
132 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"FIQ Exception at 0x%X\n\r",LR);
133 break;
134 default:
135 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Unknown Exception at 0x%X\n\r",LR);
136 break;
137 }
138 SerialPortWrite ((UINT8 *) Buffer, CharCount);
139 while(1);
140 }