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1 /** @file
2 * Main file supporting the transition to PEI Core in Normal World for Versatile Express
3 *
4 * Copyright (c) 2011, ARM Limited. All rights reserved.
5 *
6 * This program and the accompanying materials
7 * are licensed and made available under the terms and conditions of the BSD License
8 * which accompanies this distribution. The full text of the license may be found at
9 * http://opensource.org/licenses/bsd-license.php
10 *
11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 *
14 **/
15
16 #include <Library/IoLib.h>
17 #include <Library/BaseLib.h>
18 #include <Library/BaseMemoryLib.h>
19 #include <Library/PrintLib.h>
20 #include <Library/ArmLib.h>
21 #include <Library/SerialPortLib.h>
22 #include <Chipset/ArmV7.h>
23
24 #include "PrePeiCore.h"
25
26 EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mSecTemporaryRamSupportPpi = {SecTemporaryRamSupport};
27
28 EFI_PEI_PPI_DESCRIPTOR gSecPpiTable[] = {
29 {
30 EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
31 &gEfiTemporaryRamSupportPpiGuid,
32 &mSecTemporaryRamSupportPpi
33 }
34 };
35
36 VOID
37 CEntryPoint (
38 IN UINTN CoreId,
39 IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
40 )
41 {
42 //Clean Data cache
43 ArmCleanInvalidateDataCache();
44
45 //Invalidate instruction cache
46 ArmInvalidateInstructionCache();
47
48 // Enable Instruction & Data caches
49 ArmEnableDataCache ();
50 ArmEnableInstructionCache ();
51
52 //
53 // Note: Doesn't have to Enable CPU interface in non-secure world,
54 // as Non-secure interface is already enabled in Secure world.
55 //
56
57 // Write VBAR - The Vector table must be 32-byte aligned
58 ASSERT(((UINT32)PeiVectorTable & ((1 << 5)-1)) == 0);
59 ArmWriteVBar((UINT32)PeiVectorTable);
60
61 //Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.
62
63 //If not primary Jump to Secondary Main
64 if(0 == CoreId) {
65 //Goto primary Main.
66 PrimaryMain (PeiCoreEntryPoint);
67 } else {
68 SecondaryMain (CoreId);
69 }
70
71 // PEI Core should always load and never return
72 ASSERT (FALSE);
73 }
74
75 EFI_STATUS
76 EFIAPI
77 SecTemporaryRamSupport (
78 IN CONST EFI_PEI_SERVICES **PeiServices,
79 IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
80 IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
81 IN UINTN CopySize
82 )
83 {
84 //
85 // Migrate the whole temporary memory to permenent memory.
86 //
87 CopyMem (
88 (VOID*)(UINTN)PermanentMemoryBase,
89 (VOID*)(UINTN)TemporaryMemoryBase,
90 CopySize
91 );
92
93 SecSwitchStack((UINTN)(PermanentMemoryBase - TemporaryMemoryBase));
94
95 return EFI_SUCCESS;
96 }
97
98 VOID
99 PeiCommonExceptionEntry (
100 IN UINT32 Entry,
101 IN UINT32 LR
102 )
103 {
104 CHAR8 Buffer[100];
105 UINTN CharCount;
106
107 switch (Entry) {
108 case 0:
109 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reset Exception at 0x%X\n\r",LR);
110 break;
111 case 1:
112 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Undefined Exception at 0x%X\n\r",LR);
113 break;
114 case 2:
115 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"SWI Exception at 0x%X\n\r",LR);
116 break;
117 case 3:
118 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"PrefetchAbort Exception at 0x%X\n\r",LR);
119 break;
120 case 4:
121 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"DataAbort Exception at 0x%X\n\r",LR);
122 break;
123 case 5:
124 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reserved Exception at 0x%X\n\r",LR);
125 break;
126 case 6:
127 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"IRQ Exception at 0x%X\n\r",LR);
128 break;
129 case 7:
130 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"FIQ Exception at 0x%X\n\r",LR);
131 break;
132 default:
133 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Unknown Exception at 0x%X\n\r",LR);
134 break;
135 }
136 SerialPortWrite ((UINT8 *) Buffer, CharCount);
137 while(1);
138 }