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1 /** @file
2 * Main file supporting the transition to PEI Core in Normal World for Versatile Express
3 *
4 * Copyright (c) 2011, ARM Limited. All rights reserved.
5 *
6 * This program and the accompanying materials
7 * are licensed and made available under the terms and conditions of the BSD License
8 * which accompanies this distribution. The full text of the license may be found at
9 * http://opensource.org/licenses/bsd-license.php
10 *
11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 *
14 **/
15 #ifndef __PREPEICORE_H_
16 #define __PREPEICORE_H_
17
18 #include <PiPei.h>
19 #include <Ppi/TemporaryRamSupport.h>
20
21
22 EFI_STATUS
23 EFIAPI
24 SecTemporaryRamSupport (
25 IN CONST EFI_PEI_SERVICES **PeiServices,
26 IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
27 IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
28 IN UINTN CopySize
29 );
30
31 VOID
32 SecSwitchStack (
33 INTN StackDelta
34 );
35
36 // Vector Table for Pei Phase
37 VOID PeiVectorTable (VOID);
38
39 VOID
40 EFIAPI
41 PrimaryMain (
42 IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
43 );
44
45 /*
46 * This is the main function for secondary cores. They loop around until a non Null value is written to
47 * SYS_FLAGS register.The SYS_FLAGS register is platform specific.
48 * Note:The secondary cores, while executing secondary_main, assumes that:
49 * : SGI 0 is configured as Non-secure interrupt
50 * : Priority Mask is configured to allow SGI 0
51 * : Interrupt Distributor and CPU interfaces are enabled
52 *
53 */
54 VOID
55 EFIAPI
56 SecondaryMain (
57 IN UINTN CoreId
58 );
59
60 #endif