ArmPlatformPkg/PrePeiCore/PrePeiCore.h

   1 /** @file
   2 *  Main file supporting the transition to PEI Core in Normal World for Versatile Express
   3 *
   4 *  Copyright (c) 2011, ARM Limited. All rights reserved.
   5 *
   6 *  This program and the accompanying materials
   7 *  are licensed and made available under the terms and conditions of the BSD License
   8 *  which accompanies this distribution.  The full text of the license may be found at
   9 *  http://opensource.org/licenses/bsd-license.php
  10 *
  11 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 *
  14 **/
  15 #ifndef __PREPEICORE_H_
  16 #define __PREPEICORE_H_
  17
  18 #include <Library/ArmLib.h>
  19 #include <Library/ArmPlatformLib.h>
  20 #include <Library/BaseMemoryLib.h>
  21 #include <Library/DebugLib.h>
  22 #include <Library/IoLib.h>
  23 #include <Library/PcdLib.h>
  24
  25 #include <PiPei.h>
  26 #include <Ppi/TemporaryRamSupport.h>
  27
  28 VOID
  29 CreatePpiList (
  30   OUT UINTN                   *PpiListSize,
  31   OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
  32   );
  33
  34 EFI_STATUS
  35 EFIAPI
  36 PrePeiCoreTemporaryRamSupport (
  37   IN CONST EFI_PEI_SERVICES   **PeiServices,
  38   IN EFI_PHYSICAL_ADDRESS     TemporaryMemoryBase,
  39   IN EFI_PHYSICAL_ADDRESS     PermanentMemoryBase,
  40   IN UINTN                    CopySize
  41   );
  42
  43 VOID
  44 SecSwitchStack (
  45   INTN    StackDelta
  46   );
  47
  48 // Vector Table for Pei Phase
  49 VOID  PeiVectorTable (VOID);
  50
  51 VOID
  52 EFIAPI
  53 PrimaryMain (
  54   IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint
  55   );
  56
  57 /*
  58  * This is the main function for secondary cores. They loop around until a non Null value is written to
  59  * SYS_FLAGS register.The SYS_FLAGS register is platform specific.
  60  * Note:The secondary cores, while executing secondary_main, assumes that:
  61  *      : SGI 0 is configured as Non-secure interrupt
  62  *      : Priority Mask is configured to allow SGI 0
  63  *      : Interrupt Distributor and CPU interfaces are enabled
  64  *
  65  */
  66 VOID
  67 EFIAPI
  68 SecondaryMain (
  69   IN UINTN MpId
  70   );
  71
  72 VOID
  73 PeiCommonExceptionEntry (
  74   IN UINT32 Entry,
  75   IN UINTN LR
  76   );
  77
  78 #endif