ArmPlatformPkg/Sec/Sec.c

   1 /** @file
   2 *  Main file supporting the SEC Phase on ARM Platforms
   3 *
   4 *  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
   5 *
   6 *  This program and the accompanying materials
   7 *  are licensed and made available under the terms and conditions of the BSD License
   8 *  which accompanies this distribution.  The full text of the license may be found at
   9 *  http://opensource.org/licenses/bsd-license.php
  10 *
  11 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 *
  14 **/
  15
  16 #include <Library/ArmTrustedMonitorLib.h>
  17 #include <Library/DebugAgentLib.h>
  18 #include <Library/PrintLib.h>
  19 #include <Library/BaseMemoryLib.h>
  20 #include <Library/SerialPortLib.h>
  21 #include <Library/ArmGicLib.h>
  22 #include <Library/ArmCpuLib.h>
  23
  24 #include "SecInternal.h"
  25
  26 #define SerialPrint(txt)  SerialPortWrite ((UINT8*)txt, AsciiStrLen(txt)+1);
  27
  28 VOID
  29 CEntryPoint (
  30   IN  UINTN                     MpId
  31   )
  32 {
  33   CHAR8           Buffer[100];
  34   UINTN           CharCount;
  35   UINTN           JumpAddress;
  36
  37   // Invalidate the data cache. Doesn't have to do the Data cache clean.
  38   ArmInvalidateDataCache();
  39
  40   // Invalidate Instruction Cache
  41   ArmInvalidateInstructionCache();
  42
  43   // Invalidate I & D TLBs
  44   ArmInvalidateInstructionAndDataTlb();
  45
  46   // CPU specific settings
  47   ArmCpuSetup (MpId);
  48
  49   // Enable Floating Point Coprocessor if supported by the platform
  50   if (FixedPcdGet32 (PcdVFPEnabled)) {
  51     ArmEnableVFP();
  52   }
  53
  54   // Primary CPU clears out the SCU tag RAMs, secondaries wait
  55   if (IS_PRIMARY_CORE(MpId)) {
  56     if (ArmIsMpCore()) {
  57       // Signal for the initial memory is configured (event: BOOT_MEM_INIT)
  58       ArmCallSEV ();
  59     }
  60
  61     // SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib
  62     // In non SEC modules the init call is in autogenerated code.
  63     SerialPortInitialize ();
  64
  65     // Start talking
  66     if (FixedPcdGetBool (PcdTrustzoneSupport)) {
  67       CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Secure firmware (version %s built at %a on %a)\n\r",
  68           (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);
  69     } else {
  70       CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Boot firmware (version %s built at %a on %a)\n\r",
  71           (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);
  72     }
  73     SerialPortWrite ((UINT8 *) Buffer, CharCount);
  74
  75     // Initialize the Debug Agent for Source Level Debugging
  76     InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL);
  77     SaveAndSetDebugTimerInterrupt (TRUE);
  78
  79     // Now we've got UART, make the check:
  80     // - The Vector table must be 32-byte aligned
  81     ASSERT(((UINT32)SecVectorTable & ((1 << 5)-1)) == 0);
  82
  83     // Enable the GIC distributor and CPU Interface
  84     // - no other Interrupts are enabled,  doesn't have to worry about the priority.
  85     // - all the cores are in secure state, use secure SGI's
  86     ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
  87     ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
  88   } else {
  89     // Enable the GIC CPU Interface
  90     ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
  91   }
  92
  93   // Enable Full Access to CoProcessors
  94   ArmWriteCpacr (CPACR_CP_FULL_ACCESS);
  95
  96   if (IS_PRIMARY_CORE(MpId)) {
  97     // Initialize peripherals that must be done at the early stage
  98     // Example: Some L2x0 controllers must be initialized in Secure World
  99     ArmPlatformSecInitialize ();
 100
 101     // If we skip the PEI Core we could want to initialize the DRAM in the SEC phase.
 102     // If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM
 103     if (FeaturePcdGet (PcdSystemMemoryInitializeInSec)) {
 104       // Initialize system memory (DRAM)
 105       ArmPlatformInitializeSystemMemory ();
 106     }
 107   }
 108
 109   // Test if Trustzone is supported on this platform
 110   if (FixedPcdGetBool (PcdTrustzoneSupport)) {
 111     if (ArmIsMpCore()) {
 112       // Setup SMP in Non Secure world
 113       ArmCpuSetupSmpNonSecure (GET_CORE_ID(MpId));
 114     }
 115
 116     // Either we use the Secure Stacks for Secure Monitor (in this case (Base == 0) && (Size == 0))
 117     // Or we use separate Secure Monitor stacks (but (Base != 0) && (Size != 0))
 118     ASSERT (((PcdGet32(PcdCPUCoresSecMonStackBase) == 0) && (PcdGet32(PcdCPUCoreSecMonStackSize) == 0)) ||
 119             ((PcdGet32(PcdCPUCoresSecMonStackBase) != 0) && (PcdGet32(PcdCPUCoreSecMonStackSize) != 0)));
 120
 121     // Enter Monitor Mode
 122     enter_monitor_mode ((UINTN)TrustedWorldInitialization, MpId, (VOID*)(PcdGet32(PcdCPUCoresSecMonStackBase) + (PcdGet32(PcdCPUCoreSecMonStackSize) * (GET_CORE_POS(MpId) + 1))));
 123   } else {
 124     if (IS_PRIMARY_CORE(MpId)) {
 125       SerialPrint ("Trust Zone Configuration is disabled\n\r");
 126     }
 127
 128     // With Trustzone support the transition from Sec to Normal world is done by return_from_exception().
 129     // If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program
 130     // Status Register as the the current one (CPSR).
 131     copy_cpsr_into_spsr ();
 132
 133     // Call the Platform specific function to execute additional actions if required
 134     JumpAddress = PcdGet32 (PcdFvBaseAddress);
 135     ArmPlatformSecExtraAction (MpId, &JumpAddress);
 136
 137     NonTrustedWorldTransition (MpId, JumpAddress);
 138   }
 139   ASSERT (0); // We must never return from the above function
 140 }
 141
 142 VOID
 143 TrustedWorldInitialization (
 144   IN  UINTN                     MpId
 145   )
 146 {
 147   UINTN   JumpAddress;
 148
 149   //-------------------- Monitor Mode ---------------------
 150
 151   // Set up Monitor World (Vector Table, etc)
 152   ArmSecureMonitorWorldInitialize ();
 153
 154   // Transfer the interrupt to Non-secure World
 155   ArmGicSetupNonSecure (MpId, PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase));
 156
 157   // Initialize platform specific security policy
 158   ArmPlatformTrustzoneInit (MpId);
 159
 160   // Setup the Trustzone Chipsets
 161   if (IS_PRIMARY_CORE(MpId)) {
 162     if (ArmIsMpCore()) {
 163       // Signal the secondary core the Security settings is done (event: EVENT_SECURE_INIT)
 164       ArmCallSEV ();
 165     }
 166   } else {
 167     // The secondary cores need to wait until the Trustzone chipsets configuration is done
 168     // before switching to Non Secure World
 169
 170     // Wait for the Primary Core to finish the initialization of the Secure World (event: EVENT_SECURE_INIT)
 171     ArmCallWFE ();
 172   }
 173
 174   // Call the Platform specific function to execute additional actions if required
 175   JumpAddress = PcdGet32 (PcdFvBaseAddress);
 176   ArmPlatformSecExtraAction (MpId, &JumpAddress);
 177
 178   // Write to CP15 Non-secure Access Control Register
 179   ArmWriteNsacr (PcdGet32 (PcdArmNsacr));
 180
 181   // CP15 Secure Configuration Register
 182   ArmWriteScr (PcdGet32 (PcdArmScr));
 183
 184   NonTrustedWorldTransition (MpId, JumpAddress);
 185 }
 186
 187 VOID
 188 NonTrustedWorldTransition (
 189   IN  UINTN                     MpId,
 190   IN  UINTN                     JumpAddress
 191   )
 192 {
 193   // If PcdArmNonSecModeTransition is defined then set this specific mode to CPSR before the transition
 194   // By not set, the mode for Non Secure World is SVC
 195   if (PcdGet32 (PcdArmNonSecModeTransition) != 0) {
 196     set_non_secure_mode ((ARM_PROCESSOR_MODE)PcdGet32 (PcdArmNonSecModeTransition));
 197   }
 198
 199   return_from_exception (JumpAddress);
 200   //-------------------- Non Secure Mode ---------------------
 201
 202   // PEI Core should always load and never return
 203   ASSERT (FALSE);
 204 }
 205
 206 VOID
 207 SecCommonExceptionEntry (
 208   IN UINT32 Entry,
 209   IN UINT32 LR
 210   )
 211 {
 212   CHAR8           Buffer[100];
 213   UINTN           CharCount;
 214
 215   switch (Entry) {
 216   case 0:
 217     CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reset Exception at 0x%X\n\r",LR);
 218     break;
 219   case 1:
 220     CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Undefined Exception at 0x%X\n\r",LR);
 221     break;
 222   case 2:
 223     CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"SWI Exception at 0x%X\n\r",LR);
 224     break;
 225   case 3:
 226     CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"PrefetchAbort Exception at 0x%X\n\r",LR);
 227     break;
 228   case 4:
 229     CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"DataAbort Exception at 0x%X\n\r",LR);
 230     break;
 231   case 5:
 232     CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reserved Exception at 0x%X\n\r",LR);
 233     break;
 234   case 6:
 235     CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"IRQ Exception at 0x%X\n\r",LR);
 236     break;
 237   case 7:
 238     CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"FIQ Exception at 0x%X\n\r",LR);
 239     break;
 240   default:
 241     CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Unknown Exception at 0x%X\n\r",LR);
 242     break;
 243   }
 244   SerialPortWrite ((UINT8 *) Buffer, CharCount);
 245   while(1);
 246 }