ArmPlatformPkg/Sec/SecEntryPoint.S

   1 //
   2 //  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
   3 //
   4 //  This program and the accompanying materials
   5 //  are licensed and made available under the terms and conditions of the BSD License
   6 //  which accompanies this distribution.  The full text of the license may be found at
   7 //  http://opensource.org/licenses/bsd-license.php
   8 //
   9 //  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 //  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 //
  12 //
  13
  14 #include <AutoGen.h>
  15 #include <AsmMacroIoLib.h>
  16 #include "SecInternal.h"
  17
  18 .text
  19 .align 3
  20
  21 GCC_ASM_IMPORT(CEntryPoint)
  22 GCC_ASM_IMPORT(ArmPlatformSecBootAction)
  23 GCC_ASM_IMPORT(ArmPlatformSecBootMemoryInit)
  24 GCC_ASM_IMPORT(ArmDisableInterrupts)
  25 GCC_ASM_IMPORT(ArmDisableCachesAndMmu)
  26 GCC_ASM_IMPORT(ArmWriteVBar)
  27 GCC_ASM_IMPORT(ArmReadMpidr)
  28 GCC_ASM_IMPORT(SecVectorTable)
  29 GCC_ASM_IMPORT(ArmCallWFE)
  30 GCC_ASM_EXPORT(_ModuleEntryPoint)
  31
  32 StartupAddr:        .word       ASM_PFX(CEntryPoint)
  33
  34 ASM_PFX(_ModuleEntryPoint):
  35   // First ensure all interrupts are disabled
  36   bl    ASM_PFX(ArmDisableInterrupts)
  37
  38   // Ensure that the MMU and caches are off
  39   bl    ASM_PFX(ArmDisableCachesAndMmu)
  40
  41   // By default, we are doing a cold boot
  42   mov   r10, #ARM_SEC_COLD_BOOT
  43
  44   // Jump to Platform Specific Boot Action function
  45   blx   ASM_PFX(ArmPlatformSecBootAction)
  46
  47   // Set VBAR to the start of the exception vectors in Secure Mode
  48   LoadConstantToReg (ASM_PFX(SecVectorTable), r0)
  49   bl    ASM_PFX(ArmWriteVBar)
  50
  51 _IdentifyCpu:
  52   // Identify CPU ID
  53   bl    ASM_PFX(ArmReadMpidr)
  54   // Get ID of this CPU in Multicore system
  55   LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)
  56   and   r5, r0, r1
  57
  58   // Is it the Primary Core ?
  59   LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3)
  60   cmp   r5, r3
  61   // Only the primary core initialize the memory (SMC)
  62   beq   _InitMem
  63
  64 _WaitInitMem:
  65   // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized
  66   // Otherwise we have to wait the Primary Core to finish the initialization
  67   cmp   r10, #ARM_SEC_COLD_BOOT
  68   bne   _SetupSecondaryCoreStack
  69
  70   // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)
  71   bl    ASM_PFX(ArmCallWFE)
  72   // Now the Init Mem is initialized, we setup the secondary core stacks
  73   b     _SetupSecondaryCoreStack
  74
  75 _InitMem:
  76   // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized
  77   cmp   r10, #ARM_SEC_COLD_BOOT
  78   bne   _SetupPrimaryCoreStack
  79
  80   // Initialize Init Boot Memory
  81   bl    ASM_PFX(ArmPlatformSecBootMemoryInit)
  82
  83   // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)
  84   LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)
  85
  86 _SetupPrimaryCoreStack:
  87   // Get the top of the primary stacks (and the base of the secondary stacks)
  88   LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
  89   LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)
  90   add   r1, r1, r2
  91
  92   LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r2)
  93
  94   // The reserved space for global variable must be 8-bytes aligned for pushing
  95   // 64-bit variable on the stack
  96   SetPrimaryStack (r1, r2, r3)
  97   b     _PrepareArguments
  98
  99 _SetupSecondaryCoreStack:
 100   // Get the top of the primary stacks (and the base of the secondary stacks)
 101   LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
 102   LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)
 103   add   r1, r1, r2
 104
 105   // Get the Core Position (ClusterId * 4) + CoreId
 106   GetCorePositionFromMpId(r0, r5, r2)
 107   // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack
 108   add   r0, r0, #1
 109
 110   // StackOffset = CorePos * StackSize
 111   LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)
 112   mul   r0, r0, r2
 113   // SP = StackBase + StackOffset
 114   add   sp, r1, r0
 115
 116 _PrepareArguments:
 117   // Move sec startup address into a data register
 118   // Ensure we're jumping to FV version of the code (not boot remapped alias)
 119   ldr   r3, StartupAddr
 120
 121   // Jump to SEC C code
 122   //    r0 = mp_id
 123   //    r1 = Boot Mode
 124   mov   r0, r5
 125   mov   r1, r10
 126   blx   r3
 127
 128 _NeverReturn:
 129   b _NeverReturn