1 #------------------------------------------------------------------------------
3 # ARM VE Entry point. Reset vector in FV header will brach to
6 # Copyright (c) 2011, ARM Limited. All rights reserved.
8 # This program and the accompanying materials
9 # are licensed and made available under the terms and conditions of the BSD License
10 # which accompanies this distribution. The full text of the license may be found at
11 # http://opensource.org/licenses/bsd-license.php
13 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #------------------------------------------------------------------------------
18 #include <AsmMacroIoLib.h>
20 #include <Library/PcdLib.h>
21 #include <Library/ArmPlatformLib.h>
24 #Start of Code section
28 #make _ModuleEntryPoint as global
29 GCC_ASM_EXPORT(_ModuleEntryPoint)
31 #global functions referenced by this module
32 GCC_ASM_IMPORT(CEntryPoint)
33 GCC_ASM_IMPORT(ArmPlatformIsMemoryInitialized)
34 GCC_ASM_IMPORT(ArmPlatformInitializeBootMemory)
35 GCC_ASM_IMPORT(ArmDisableInterrupts)
36 GCC_ASM_IMPORT(ArmDisableCachesAndMmu)
37 GCC_ASM_IMPORT(ArmWriteVBar)
38 GCC_ASM_IMPORT(ArmReadMpidr)
39 GCC_ASM_IMPORT(SecVectorTable)
41 #if (FixedPcdGet32(PcdMPCoreSupport))
42 GCC_ASM_IMPORT(ArmIsScuEnable)
45 StartupAddr: .word ASM_PFX(CEntryPoint)
46 SecVectorTableAddr: .word ASM_PFX(SecVectorTable)
48 ASM_PFX(_ModuleEntryPoint):
49 #Set VBAR to the start of the exception vectors in Secure Mode
50 ldr r0, SecVectorTableAddr
51 bl ASM_PFX(ArmWriteVBar)
53 # First ensure all interrupts are disabled
54 bl ASM_PFX(ArmDisableInterrupts)
56 # Ensure that the MMU and caches are off
57 bl ASM_PFX(ArmDisableCachesAndMmu)
61 bl ASM_PFX(ArmReadMpidr)
62 // Get ID of this CPU in Multicore system
63 LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)
66 #get ID of this CPU in Multicore system
67 LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r1)
69 # Only the primary core initialize the memory (SMC)
72 #if (FixedPcdGet32(PcdMPCoreSupport))
73 # ... The secondary cores wait for SCU to be enabled
75 bl ASM_PFX(ArmIsScuEnable)
77 beq _WaitForEnabledScu
82 bl ASM_PFX(ArmPlatformIsMemoryInitialized)
85 # Initialize Init Memory
86 bl ASM_PFX(ArmPlatformInitializeBootMemory)
88 # Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)
92 # Setup Stack for the 4 CPU cores
93 #Read Stack Base address from PCD
94 LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
96 #read Stack size from PCD
97 LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecStackSize), r2)
99 #calcuate Stack Pointer reg value using Stack size and CPU ID.
100 mov r3,r5 @ r3 = core_id
101 mul r3,r3,r2 @ r3 = core_id * stack_size = offset from the stack base
102 add r3,r3,r1 @ r3 ldr= stack_base + offset
105 # move sec startup address into a data register
106 # ensure we're jumping to FV version of the code (not boot remapped alias)
109 # Move the CoreId in r0 to be the first argument of the SEC Entry Point