ArmPlatformPkg/Sec/SecEntryPoint.asm

   1 //
   2 //  Copyright (c) 2011, ARM Limited. All rights reserved.
   3 //
   4 //  This program and the accompanying materials
   5 //  are licensed and made available under the terms and conditions of the BSD License
   6 //  which accompanies this distribution.  The full text of the license may be found at
   7 //  http://opensource.org/licenses/bsd-license.php
   8 //
   9 //  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 //  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 //
  12 //
  13
  14 #include <AutoGen.h>
  15 #include <AsmMacroIoLib.h>
  16 #include <Base.h>
  17 #include <Library/PcdLib.h>
  18 #include <Library/ArmPlatformLib.h>
  19
  20   INCLUDE AsmMacroIoLib.inc
  21
  22   IMPORT  CEntryPoint
  23   IMPORT  ArmPlatformSecBootAction
  24   IMPORT  ArmPlatformIsMemoryInitialized
  25   IMPORT  ArmPlatformInitializeBootMemory
  26   IMPORT  ArmDisableInterrupts
  27   IMPORT  ArmDisableCachesAndMmu
  28   IMPORT  ArmWriteVBar
  29   IMPORT  ArmReadMpidr
  30   IMPORT  SecVectorTable
  31   EXPORT  _ModuleEntryPoint
  32
  33 #if (FixedPcdGet32(PcdMPCoreSupport))
  34   IMPORT  ArmIsScuEnable
  35 #endif
  36
  37   PRESERVE8
  38   AREA    SecEntryPoint, CODE, READONLY
  39
  40 StartupAddr        DCD      CEntryPoint
  41
  42 _ModuleEntryPoint
  43   // First ensure all interrupts are disabled
  44   blx   ArmDisableInterrupts
  45
  46   // Ensure that the MMU and caches are off
  47   blx   ArmDisableCachesAndMmu
  48
  49   // Jump to Platform Specific Boot Action function
  50   blx   ArmPlatformSecBootAction
  51
  52   // Set VBAR to the start of the exception vectors in Secure Mode
  53   ldr   r0, =SecVectorTable
  54   blx   ArmWriteVBar
  55
  56 _IdentifyCpu
  57   // Identify CPU ID
  58   bl    ArmReadMpidr
  59   // Get ID of this CPU in Multicore system
  60   LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)
  61   and   r5, r0, r1
  62
  63   // Is it the Primary Core ?
  64   LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r1)
  65   cmp   r5, r1
  66   // Only the primary core initialize the memory (SMC)
  67   beq   _InitMem
  68
  69 #if (FixedPcdGet32(PcdMPCoreSupport))
  70   // ... The secondary cores wait for SCU to be enabled
  71 _WaitForEnabledScu
  72   bl    ArmIsScuEnable
  73   tst   r1, #1
  74   beq   _WaitForEnabledScu
  75   b     _SetupStack
  76 #endif
  77
  78 _InitMem
  79   bl    ArmPlatformIsMemoryInitialized
  80   bne   _SetupStack
  81
  82   // Initialize Init Memory
  83   bl    ArmPlatformInitializeBootMemory
  84
  85   // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)
  86   mov   r5, #0
  87
  88 _SetupStack
  89   // Setup Stack for the 4 CPU cores
  90   //Read Stack Base address from PCD
  91   LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
  92
  93   // Read Stack size from PCD
  94   LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecStackSize), r2)
  95
  96   // Calcuate Stack Pointer reg value using Stack size and CPU ID.
  97   mov     r3,r5         // r3 = core_id
  98   mul     r3,r3,r2      // r3 = core_id * stack_size = offset from the stack base
  99   add     r3,r3,r1      // r3 = stack_base + offset
 100   mov     sp, r3
 101
 102   // Move sec startup address into a data register
 103   // ensure we're jumping to FV version of the code (not boot remapped alias)
 104   ldr   r3, StartupAddr
 105
 106   // Jump to SEC C code
 107   //    r0 = mp_id
 108   mov   r0, r5
 109   blx   r3
 110
 111   END