ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c

   1 /** @file
   2   ArmGicArchLib library class implementation for DT based virt platforms
   3
   4   Copyright (c) 2015 - 2016, Linaro Ltd. All rights reserved.<BR>
   5
   6   This program and the accompanying materials
   7   are licensed and made available under the terms and conditions of the BSD License
   8   which accompanies this distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #include <Base.h>
  17 #include <Uefi.h>
  18
  19 #include <Library/ArmGicLib.h>
  20 #include <Library/ArmGicArchLib.h>
  21 #include <Library/BaseLib.h>
  22 #include <Library/DebugLib.h>
  23 #include <Library/PcdLib.h>
  24 #include <Library/UefiBootServicesTableLib.h>
  25
  26 #include <Protocol/FdtClient.h>
  27
  28 STATIC ARM_GIC_ARCH_REVISION        mGicArchRevision;
  29
  30 RETURN_STATUS
  31 EFIAPI
  32 ArmVirtGicArchLibConstructor (
  33   VOID
  34   )
  35 {
  36   UINT32                IccSre;
  37   FDT_CLIENT_PROTOCOL   *FdtClient;
  38   CONST UINT64          *Reg;
  39   UINT32                RegSize;
  40   UINTN                 AddressCells, SizeCells;
  41   UINTN                 GicRevision;
  42   EFI_STATUS            Status;
  43   UINT64                DistBase, CpuBase, RedistBase;
  44
  45   Status = gBS->LocateProtocol (&gFdtClientProtocolGuid, NULL,
  46                   (VOID **)&FdtClient);
  47   ASSERT_EFI_ERROR (Status);
  48
  49   GicRevision = 2;
  50   Status = FdtClient->FindCompatibleNodeReg (FdtClient, "arm,cortex-a15-gic",
  51                         (CONST VOID **)&Reg, &AddressCells, &SizeCells,
  52                         &RegSize);
  53   if (Status == EFI_NOT_FOUND) {
  54     GicRevision = 3;
  55     Status = FdtClient->FindCompatibleNodeReg (FdtClient, "arm,gic-v3",
  56                           (CONST VOID **)&Reg, &AddressCells, &SizeCells,
  57                           &RegSize);
  58   }
  59   if (EFI_ERROR (Status)) {
  60     return Status;
  61   }
  62
  63   switch (GicRevision) {
  64
  65   case 3:
  66     //
  67     // The GIC v3 DT binding describes a series of at least 3 physical (base
  68     // addresses, size) pairs: the distributor interface (GICD), at least one
  69     // redistributor region (GICR) containing dedicated redistributor
  70     // interfaces for all individual CPUs, and the CPU interface (GICC).
  71     // Under virtualization, we assume that the first redistributor region
  72     // listed covers the boot CPU. Also, our GICv3 driver only supports the
  73     // system register CPU interface, so we can safely ignore the MMIO version
  74     // which is listed after the sequence of redistributor interfaces.
  75     // This means we are only interested in the first two memory regions
  76     // supplied, and ignore everything else.
  77     //
  78     ASSERT (RegSize >= 32);
  79
  80     // RegProp[0..1] == { GICD base, GICD size }
  81     DistBase = SwapBytes64 (Reg[0]);
  82     ASSERT (DistBase < MAX_UINT32);
  83
  84     // RegProp[2..3] == { GICR base, GICR size }
  85     RedistBase = SwapBytes64 (Reg[2]);
  86     ASSERT (RedistBase < MAX_UINT32);
  87
  88     PcdSet64 (PcdGicDistributorBase, DistBase);
  89     PcdSet64 (PcdGicRedistributorsBase, RedistBase);
  90
  91     DEBUG ((EFI_D_INFO, "Found GIC v3 (re)distributor @ 0x%Lx (0x%Lx)\n",
  92       DistBase, RedistBase));
  93
  94     //
  95     // The default implementation of ArmGicArchLib is responsible for enabling
  96     // the system register interface on the GICv3 if one is found. So let's do
  97     // the same here.
  98     //
  99     IccSre = ArmGicV3GetControlSystemRegisterEnable ();
 100     if (!(IccSre & ICC_SRE_EL2_SRE)) {
 101       ArmGicV3SetControlSystemRegisterEnable (IccSre | ICC_SRE_EL2_SRE);
 102       IccSre = ArmGicV3GetControlSystemRegisterEnable ();
 103     }
 104
 105     //
 106     // Unlike the default implementation, there is no fall through to GICv2
 107     // mode if this GICv3 cannot be driven in native mode due to the fact
 108     // that the System Register interface is unavailable.
 109     //
 110     ASSERT (IccSre & ICC_SRE_EL2_SRE);
 111
 112     mGicArchRevision = ARM_GIC_ARCH_REVISION_3;
 113     break;
 114
 115   case 2:
 116     ASSERT (RegSize == 32);
 117
 118     DistBase = SwapBytes64 (Reg[0]);
 119     CpuBase  = SwapBytes64 (Reg[2]);
 120     ASSERT (DistBase < MAX_UINT32);
 121     ASSERT (CpuBase < MAX_UINT32);
 122
 123     PcdSet64 (PcdGicDistributorBase, DistBase);
 124     PcdSet64 (PcdGicInterruptInterfaceBase, CpuBase);
 125
 126     DEBUG ((EFI_D_INFO, "Found GIC @ 0x%Lx/0x%Lx\n", DistBase, CpuBase));
 127
 128     mGicArchRevision = ARM_GIC_ARCH_REVISION_2;
 129     break;
 130
 131   default:
 132     DEBUG ((EFI_D_ERROR, "%a: No GIC revision specified!\n", __FUNCTION__));
 133     return RETURN_NOT_FOUND;
 134   }
 135   return RETURN_SUCCESS;
 136 }
 137
 138 ARM_GIC_ARCH_REVISION
 139 EFIAPI
 140 ArmGicGetSupportedArchRevision (
 141   VOID
 142   )
 143 {
 144   return mGicArchRevision;
 145 }