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1 /** @file
2 Provides the basic interfaces to abstract a PCI Host Bridge Resource Allocation
3
4 Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials are
6 licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #include "PciHostBridge.h"
16
17 //
18 // Hard code: Root Bridge Number within the host bridge
19 // Root Bridge's attribute
20 // Root Bridge's device path
21 // Root Bridge's resource aperture
22 //
23 UINTN RootBridgeNumber[1] = { 1 };
24
25 UINT64 RootBridgeAttribute[1][1] = { { EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM } };
26
27 EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[1][1] = {
28 {
29 {
30 {
31 {
32 ACPI_DEVICE_PATH,
33 ACPI_DP,
34 {
35 (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
36 (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
37 }
38 },
39 EISA_PNP_ID(0x0A03),
40 0
41 },
42
43 {
44 END_DEVICE_PATH_TYPE,
45 END_ENTIRE_DEVICE_PATH_SUBTYPE,
46 {
47 END_DEVICE_PATH_LENGTH,
48 0
49 }
50 }
51 }
52 }
53 };
54
55 STATIC PCI_ROOT_BRIDGE_RESOURCE_APERTURE mResAperture[1][1];
56
57 EFI_HANDLE mDriverImageHandle;
58
59 PCI_HOST_BRIDGE_INSTANCE mPciHostBridgeInstanceTemplate = {
60 PCI_HOST_BRIDGE_SIGNATURE, // Signature
61 NULL, // HostBridgeHandle
62 0, // RootBridgeNumber
63 {NULL, NULL}, // Head
64 FALSE, // ResourceSubiteed
65 TRUE, // CanRestarted
66 {
67 NotifyPhase,
68 GetNextRootBridge,
69 GetAttributes,
70 StartBusEnumeration,
71 SetBusNumbers,
72 SubmitResources,
73 GetProposedResources,
74 PreprocessController
75 }
76 };
77
78 //
79 // Implementation
80 //
81
82 STATIC
83 VOID
84 SetLinuxPciProbeOnlyProperty (
85 IN FDT_CLIENT_PROTOCOL *FdtClient
86 )
87 {
88 INT32 Node;
89 UINT32 Tmp;
90 EFI_STATUS Status;
91
92 if (!FeaturePcdGet (PcdPureAcpiBoot)) {
93 //
94 // Set the /chosen/linux,pci-probe-only property to 1, so that the PCI
95 // setup we will perform in the firmware is honored by the Linux OS,
96 // rather than torn down and done from scratch. This is generally a more
97 // sensible approach, and aligns with what ACPI based OSes do typically.
98 //
99 // In case we are exposing an emulated VGA PCI device to the guest, which
100 // may subsequently get exposed via the Graphics Output protocol and
101 // driven as an efifb by Linux, we need this setting to prevent the
102 // framebuffer from becoming unresponsive.
103 //
104 Status = FdtClient->GetOrInsertChosenNode (FdtClient, &Node);
105
106 if (!EFI_ERROR (Status)) {
107 Tmp = SwapBytes32 (1);
108 Status = FdtClient->SetNodeProperty (FdtClient, Node,
109 "linux,pci-probe-only", &Tmp, sizeof (Tmp));
110 }
111 if (EFI_ERROR (Status)) {
112 DEBUG ((EFI_D_WARN,
113 "Failed to set /chosen/linux,pci-probe-only property\n"));
114 }
115 }
116 }
117
118 //
119 // We expect the "ranges" property of "pci-host-ecam-generic" to consist of
120 // records like this.
121 //
122 #pragma pack (1)
123 typedef struct {
124 UINT32 Type;
125 UINT64 ChildBase;
126 UINT64 CpuBase;
127 UINT64 Size;
128 } DTB_PCI_HOST_RANGE_RECORD;
129 #pragma pack ()
130
131 #define DTB_PCI_HOST_RANGE_RELOCATABLE BIT31
132 #define DTB_PCI_HOST_RANGE_PREFETCHABLE BIT30
133 #define DTB_PCI_HOST_RANGE_ALIASED BIT29
134 #define DTB_PCI_HOST_RANGE_MMIO32 BIT25
135 #define DTB_PCI_HOST_RANGE_MMIO64 (BIT25 | BIT24)
136 #define DTB_PCI_HOST_RANGE_IO BIT24
137 #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
138
139 STATIC
140 EFI_STATUS
141 ProcessPciHost (
142 OUT UINT64 *IoBase,
143 OUT UINT64 *IoSize,
144 OUT UINT64 *IoTranslation,
145 OUT UINT64 *MmioBase,
146 OUT UINT64 *MmioSize,
147 OUT UINT64 *MmioTranslation,
148 OUT UINT32 *BusMin,
149 OUT UINT32 *BusMax
150 )
151 {
152 FDT_CLIENT_PROTOCOL *FdtClient;
153 INT32 Node;
154 UINT64 ConfigBase, ConfigSize;
155 CONST VOID *Prop;
156 UINT32 Len;
157 UINT32 RecordIdx;
158 EFI_STATUS Status;
159
160 //
161 // The following output arguments are initialized only in
162 // order to suppress '-Werror=maybe-uninitialized' warnings
163 // *incorrectly* emitted by some gcc versions.
164 //
165 *IoBase = 0;
166 *IoTranslation = 0;
167 *MmioBase = 0;
168 *MmioTranslation = 0;
169 *BusMin = 0;
170 *BusMax = 0;
171
172 //
173 // *IoSize and *MmioSize are initialized to zero because the logic below
174 // requires it. However, since they are also affected by the issue reported
175 // above, they are initialized early.
176 //
177 *IoSize = 0;
178 *MmioSize = 0;
179
180 Status = gBS->LocateProtocol (&gFdtClientProtocolGuid, NULL,
181 (VOID **)&FdtClient);
182 ASSERT_EFI_ERROR (Status);
183
184 Status = FdtClient->FindCompatibleNode (FdtClient, "pci-host-ecam-generic",
185 &Node);
186 if (EFI_ERROR (Status)) {
187 DEBUG ((EFI_D_INFO,
188 "%a: No 'pci-host-ecam-generic' compatible DT node found\n",
189 __FUNCTION__));
190 return EFI_NOT_FOUND;
191 }
192
193 DEBUG_CODE (
194 INT32 Tmp;
195
196 //
197 // A DT can legally describe multiple PCI host bridges, but we are not
198 // equipped to deal with that. So assert that there is only one.
199 //
200 Status = FdtClient->FindNextCompatibleNode (FdtClient,
201 "pci-host-ecam-generic", Node, &Tmp);
202 ASSERT (Status == EFI_NOT_FOUND);
203 );
204
205 Status = FdtClient->GetNodeProperty (FdtClient, Node, "reg", &Prop, &Len);
206 if (EFI_ERROR (Status) || Len != 2 * sizeof (UINT64)) {
207 DEBUG ((EFI_D_ERROR, "%a: 'reg' property not found or invalid\n",
208 __FUNCTION__));
209 return EFI_PROTOCOL_ERROR;
210 }
211
212 //
213 // Fetch the ECAM window.
214 //
215 ConfigBase = SwapBytes64 (((CONST UINT64 *)Prop)[0]);
216 ConfigSize = SwapBytes64 (((CONST UINT64 *)Prop)[1]);
217
218 //
219 // Fetch the bus range (note: inclusive).
220 //
221 Status = FdtClient->GetNodeProperty (FdtClient, Node, "bus-range", &Prop,
222 &Len);
223 if (EFI_ERROR (Status) || Len != 2 * sizeof (UINT32)) {
224 DEBUG ((EFI_D_ERROR, "%a: 'bus-range' not found or invalid\n",
225 __FUNCTION__));
226 return EFI_PROTOCOL_ERROR;
227 }
228 *BusMin = SwapBytes32 (((CONST UINT32 *)Prop)[0]);
229 *BusMax = SwapBytes32 (((CONST UINT32 *)Prop)[1]);
230
231 //
232 // Sanity check: the config space must accommodate all 4K register bytes of
233 // all 8 functions of all 32 devices of all buses.
234 //
235 if (*BusMax < *BusMin || *BusMax - *BusMin == MAX_UINT32 ||
236 DivU64x32 (ConfigSize, SIZE_4KB * 8 * 32) < *BusMax - *BusMin + 1) {
237 DEBUG ((EFI_D_ERROR, "%a: invalid 'bus-range' and/or 'reg'\n",
238 __FUNCTION__));
239 return EFI_PROTOCOL_ERROR;
240 }
241
242 //
243 // Iterate over "ranges".
244 //
245 Status = FdtClient->GetNodeProperty (FdtClient, Node, "ranges", &Prop, &Len);
246 if (EFI_ERROR (Status) || Len == 0 ||
247 Len % sizeof (DTB_PCI_HOST_RANGE_RECORD) != 0) {
248 DEBUG ((EFI_D_ERROR, "%a: 'ranges' not found or invalid\n", __FUNCTION__));
249 return EFI_PROTOCOL_ERROR;
250 }
251
252 for (RecordIdx = 0; RecordIdx < Len / sizeof (DTB_PCI_HOST_RANGE_RECORD);
253 ++RecordIdx) {
254 CONST DTB_PCI_HOST_RANGE_RECORD *Record;
255
256 Record = (CONST DTB_PCI_HOST_RANGE_RECORD *)Prop + RecordIdx;
257 switch (SwapBytes32 (Record->Type) & DTB_PCI_HOST_RANGE_TYPEMASK) {
258 case DTB_PCI_HOST_RANGE_IO:
259 *IoBase = SwapBytes64 (Record->ChildBase);
260 *IoSize = SwapBytes64 (Record->Size);
261 *IoTranslation = SwapBytes64 (Record->CpuBase) - *IoBase;
262 break;
263
264 case DTB_PCI_HOST_RANGE_MMIO32:
265 *MmioBase = SwapBytes64 (Record->ChildBase);
266 *MmioSize = SwapBytes64 (Record->Size);
267 *MmioTranslation = SwapBytes64 (Record->CpuBase) - *MmioBase;
268
269 if (*MmioBase > MAX_UINT32 || *MmioSize > MAX_UINT32 ||
270 *MmioBase + *MmioSize > SIZE_4GB) {
271 DEBUG ((EFI_D_ERROR, "%a: MMIO32 space invalid\n", __FUNCTION__));
272 return EFI_PROTOCOL_ERROR;
273 }
274
275 if (*MmioTranslation != 0) {
276 DEBUG ((EFI_D_ERROR, "%a: unsupported nonzero MMIO32 translation "
277 "0x%Lx\n", __FUNCTION__, *MmioTranslation));
278 return EFI_UNSUPPORTED;
279 }
280
281 break;
282 }
283 }
284 if (*IoSize == 0 || *MmioSize == 0) {
285 DEBUG ((EFI_D_ERROR, "%a: %a space empty\n", __FUNCTION__,
286 (*IoSize == 0) ? "IO" : "MMIO32"));
287 return EFI_PROTOCOL_ERROR;
288 }
289
290 //
291 // The dynamic PCD PcdPciExpressBaseAddress should have already been set,
292 // and should match the value we found in the DT node.
293 //
294 ASSERT (PcdGet64 (PcdPciExpressBaseAddress) == ConfigBase);
295
296 SetLinuxPciProbeOnlyProperty (FdtClient);
297
298 DEBUG ((EFI_D_INFO, "%a: Config[0x%Lx+0x%Lx) Bus[0x%x..0x%x] "
299 "Io[0x%Lx+0x%Lx)@0x%Lx Mem[0x%Lx+0x%Lx)@0x%Lx\n", __FUNCTION__, ConfigBase,
300 ConfigSize, *BusMin, *BusMax, *IoBase, *IoSize, *IoTranslation, *MmioBase,
301 *MmioSize, *MmioTranslation));
302 return EFI_SUCCESS;
303 }
304
305
306 /**
307 Entry point of this driver
308
309 @param ImageHandle Handle of driver image
310 @param SystemTable Point to EFI_SYSTEM_TABLE
311
312 @retval EFI_ABORTED PCI host bridge not present
313 @retval EFI_OUT_OF_RESOURCES Can not allocate memory resource
314 @retval EFI_DEVICE_ERROR Can not install the protocol instance
315 @retval EFI_SUCCESS Success to initialize the Pci host bridge.
316 **/
317 EFI_STATUS
318 EFIAPI
319 InitializePciHostBridge (
320 IN EFI_HANDLE ImageHandle,
321 IN EFI_SYSTEM_TABLE *SystemTable
322 )
323 {
324 UINT64 MmioAttributes;
325 EFI_STATUS Status;
326 UINTN Loop1;
327 UINTN Loop2;
328 PCI_HOST_BRIDGE_INSTANCE *HostBridge;
329 PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
330 UINT64 IoBase, IoSize, IoTranslation;
331 UINT64 MmioBase, MmioSize, MmioTranslation;
332 UINT32 BusMin, BusMax;
333
334 if (PcdGet64 (PcdPciExpressBaseAddress) == 0) {
335 DEBUG ((EFI_D_INFO, "%a: PCI host bridge not present\n", __FUNCTION__));
336 return EFI_ABORTED;
337 }
338
339 Status = ProcessPciHost (&IoBase, &IoSize, &IoTranslation, &MmioBase,
340 &MmioSize, &MmioTranslation, &BusMin, &BusMax);
341 if (EFI_ERROR (Status)) {
342 return Status;
343 }
344
345 mDriverImageHandle = ImageHandle;
346
347 mResAperture[0][0].BusBase = BusMin;
348 mResAperture[0][0].BusLimit = BusMax;
349
350 mResAperture[0][0].MemBase = MmioBase;
351 mResAperture[0][0].MemLimit = MmioBase + MmioSize - 1;
352
353 mResAperture[0][0].IoBase = IoBase;
354 mResAperture[0][0].IoLimit = IoBase + IoSize - 1;
355 mResAperture[0][0].IoTranslation = IoTranslation;
356
357 //
358 // Add IO and MMIO memory space, so that resources can be allocated in the
359 // EfiPciHostBridgeAllocateResources phase.
360 //
361 Status = gDS->AddIoSpace (
362 EfiGcdIoTypeIo,
363 IoBase,
364 IoSize
365 );
366 ASSERT_EFI_ERROR (Status);
367
368 MmioAttributes = FeaturePcdGet (PcdKludgeMapPciMmioAsCached) ?
369 EFI_MEMORY_WB : EFI_MEMORY_UC;
370
371 Status = gDS->AddMemorySpace (
372 EfiGcdMemoryTypeMemoryMappedIo,
373 MmioBase,
374 MmioSize,
375 MmioAttributes
376 );
377 if (EFI_ERROR (Status)) {
378 DEBUG ((EFI_D_ERROR, "%a: AddMemorySpace: %r\n", __FUNCTION__, Status));
379 return Status;
380 }
381
382 Status = gDS->SetMemorySpaceAttributes (
383 MmioBase,
384 MmioSize,
385 MmioAttributes
386 );
387 if (EFI_ERROR (Status)) {
388 DEBUG ((EFI_D_ERROR, "%a: SetMemorySpaceAttributes: %r\n", __FUNCTION__,
389 Status));
390 return Status;
391 }
392
393 //
394 // Create Host Bridge Device Handle
395 //
396 for (Loop1 = 0; Loop1 < HOST_BRIDGE_NUMBER; Loop1++) {
397 HostBridge = AllocateCopyPool (sizeof(PCI_HOST_BRIDGE_INSTANCE), &mPciHostBridgeInstanceTemplate);
398 if (HostBridge == NULL) {
399 return EFI_OUT_OF_RESOURCES;
400 }
401
402 HostBridge->RootBridgeNumber = RootBridgeNumber[Loop1];
403 InitializeListHead (&HostBridge->Head);
404
405 Status = gBS->InstallMultipleProtocolInterfaces (
406 &HostBridge->HostBridgeHandle,
407 &gEfiPciHostBridgeResourceAllocationProtocolGuid, &HostBridge->ResAlloc,
408 NULL
409 );
410 if (EFI_ERROR (Status)) {
411 FreePool (HostBridge);
412 return EFI_DEVICE_ERROR;
413 }
414
415 //
416 // Create Root Bridge Device Handle in this Host Bridge
417 //
418
419 for (Loop2 = 0; Loop2 < HostBridge->RootBridgeNumber; Loop2++) {
420 PrivateData = AllocateZeroPool (sizeof(PCI_ROOT_BRIDGE_INSTANCE));
421 if (PrivateData == NULL) {
422 return EFI_OUT_OF_RESOURCES;
423 }
424
425 PrivateData->Signature = PCI_ROOT_BRIDGE_SIGNATURE;
426 PrivateData->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[Loop1][Loop2];
427
428 RootBridgeConstructor (
429 &PrivateData->Io,
430 HostBridge->HostBridgeHandle,
431 RootBridgeAttribute[Loop1][Loop2],
432 &mResAperture[Loop1][Loop2]
433 );
434
435 Status = gBS->InstallMultipleProtocolInterfaces(
436 &PrivateData->Handle,
437 &gEfiDevicePathProtocolGuid, PrivateData->DevicePath,
438 &gEfiPciRootBridgeIoProtocolGuid, &PrivateData->Io,
439 NULL
440 );
441 if (EFI_ERROR (Status)) {
442 FreePool(PrivateData);
443 return EFI_DEVICE_ERROR;
444 }
445
446 InsertTailList (&HostBridge->Head, &PrivateData->Link);
447 }
448 }
449
450 return EFI_SUCCESS;
451 }
452
453
454 /**
455 These are the notifications from the PCI bus driver that it is about to enter a certain
456 phase of the PCI enumeration process.
457
458 This member function can be used to notify the host bridge driver to perform specific actions,
459 including any chipset-specific initialization, so that the chipset is ready to enter the next phase.
460 Eight notification points are defined at this time. See belows:
461 EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures and internal data
462 structures. The PCI enumerator should issue this notification
463 before starting a fresh enumeration process. Enumeration cannot
464 be restarted after sending any other notification such as
465 EfiPciHostBridgeBeginBusAllocation.
466 EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to begin. No specific action is
467 required here. This notification can be used to perform any
468 chipset-specific programming.
469 EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming phase is complete. No
470 specific action is required here. This notification can be used to
471 perform any chipset-specific programming.
472 EfiPciHostBridgeBeginResourceAllocation
473 The resource allocation phase is about to begin. No specific
474 action is required here. This notification can be used to perform
475 any chipset-specific programming.
476 EfiPciHostBridgeAllocateResources Allocates resources per previously submitted requests for all the PCI
477 root bridges. These resource settings are returned on the next call to
478 GetProposedResources(). Before calling NotifyPhase() with a Phase of
479 EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible
480 for gathering I/O and memory requests for
481 all the PCI root bridges and submitting these requests using
482 SubmitResources(). This function pads the resource amount
483 to suit the root bridge hardware, takes care of dependencies between
484 the PCI root bridges, and calls the Global Coherency Domain (GCD)
485 with the allocation request. In the case of padding, the allocated range
486 could be bigger than what was requested.
487 EfiPciHostBridgeSetResources Programs the host bridge hardware to decode previously allocated
488 resources (proposed resources) for all the PCI root bridges. After the
489 hardware is programmed, reassigning resources will not be supported.
490 The bus settings are not affected.
491 EfiPciHostBridgeFreeResources Deallocates resources that were previously allocated for all the PCI
492 root bridges and resets the I/O and memory apertures to their initial
493 state. The bus settings are not affected. If the request to allocate
494 resources fails, the PCI enumerator can use this notification to
495 deallocate previous resources, adjust the requests, and retry
496 allocation.
497 EfiPciHostBridgeEndResourceAllocation The resource allocation phase is completed. No specific action is
498 required here. This notification can be used to perform any chipsetspecific
499 programming.
500
501 @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
502 @param[in] Phase The phase during enumeration
503
504 @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error
505 is valid for a Phase of EfiPciHostBridgeAllocateResources if
506 SubmitResources() has not been called for one or more
507 PCI root bridges before this call
508 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid
509 for a Phase of EfiPciHostBridgeSetResources.
510 @retval EFI_INVALID_PARAMETER Invalid phase parameter
511 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
512 This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the
513 previously submitted resource requests cannot be fulfilled or
514 were only partially fulfilled.
515 @retval EFI_SUCCESS The notification was accepted without any errors.
516
517 **/
518 EFI_STATUS
519 EFIAPI
520 NotifyPhase(
521 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
522 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
523 )
524 {
525 PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
526 PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
527 PCI_RESOURCE_TYPE Index;
528 LIST_ENTRY *List;
529 EFI_PHYSICAL_ADDRESS BaseAddress;
530 UINT64 AddrLen;
531 UINTN BitsOfAlignment;
532 EFI_STATUS Status;
533 EFI_STATUS ReturnStatus;
534
535 HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
536
537 switch (Phase) {
538
539 case EfiPciHostBridgeBeginEnumeration:
540 if (HostBridgeInstance->CanRestarted) {
541 //
542 // Reset the Each Root Bridge
543 //
544 List = HostBridgeInstance->Head.ForwardLink;
545
546 while (List != &HostBridgeInstance->Head) {
547 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
548 for (Index = TypeIo; Index < TypeMax; Index++) {
549 RootBridgeInstance->ResAllocNode[Index].Type = Index;
550 RootBridgeInstance->ResAllocNode[Index].Base = 0;
551 RootBridgeInstance->ResAllocNode[Index].Length = 0;
552 RootBridgeInstance->ResAllocNode[Index].Status = ResNone;
553 }
554
555 List = List->ForwardLink;
556 }
557
558 HostBridgeInstance->ResourceSubmited = FALSE;
559 HostBridgeInstance->CanRestarted = TRUE;
560 } else {
561 //
562 // Can not restart
563 //
564 return EFI_NOT_READY;
565 }
566 break;
567
568 case EfiPciHostBridgeEndEnumeration:
569 break;
570
571 case EfiPciHostBridgeBeginBusAllocation:
572 //
573 // No specific action is required here, can perform any chipset specific programing
574 //
575 HostBridgeInstance->CanRestarted = FALSE;
576 break;
577
578 case EfiPciHostBridgeEndBusAllocation:
579 //
580 // No specific action is required here, can perform any chipset specific programing
581 //
582 //HostBridgeInstance->CanRestarted = FALSE;
583 break;
584
585 case EfiPciHostBridgeBeginResourceAllocation:
586 //
587 // No specific action is required here, can perform any chipset specific programing
588 //
589 //HostBridgeInstance->CanRestarted = FALSE;
590 break;
591
592 case EfiPciHostBridgeAllocateResources:
593 ReturnStatus = EFI_SUCCESS;
594 if (HostBridgeInstance->ResourceSubmited) {
595 //
596 // Take care of the resource dependencies between the root bridges
597 //
598 List = HostBridgeInstance->Head.ForwardLink;
599
600 while (List != &HostBridgeInstance->Head) {
601 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
602 for (Index = TypeIo; Index < TypeBus; Index++) {
603 if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {
604
605 AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
606
607 //
608 // Get the number of '1' in Alignment.
609 //
610 BitsOfAlignment = (UINTN) (HighBitSet64 (RootBridgeInstance->ResAllocNode[Index].Alignment) + 1);
611
612 switch (Index) {
613
614 case TypeIo:
615 //
616 // It is impossible for this chipset to align 0xFFFF for IO16
617 // So clear it
618 //
619 if (BitsOfAlignment >= 16) {
620 BitsOfAlignment = 0;
621 }
622
623 BaseAddress = mResAperture[0][0].IoLimit;
624 Status = gDS->AllocateIoSpace (
625 EfiGcdAllocateMaxAddressSearchTopDown,
626 EfiGcdIoTypeIo,
627 BitsOfAlignment,
628 AddrLen,
629 &BaseAddress,
630 mDriverImageHandle,
631 NULL
632 );
633
634 if (!EFI_ERROR (Status)) {
635 RootBridgeInstance->ResAllocNode[Index].Base = (UINTN)BaseAddress;
636 RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated;
637 } else {
638 ReturnStatus = Status;
639 if (Status != EFI_OUT_OF_RESOURCES) {
640 RootBridgeInstance->ResAllocNode[Index].Length = 0;
641 }
642 }
643
644 break;
645
646
647 case TypeMem32:
648 //
649 // It is impossible for this chipset to align 0xFFFFFFFF for Mem32
650 // So clear it
651 //
652
653 if (BitsOfAlignment >= 32) {
654 BitsOfAlignment = 0;
655 }
656
657 BaseAddress = mResAperture[0][0].MemLimit;
658 Status = gDS->AllocateMemorySpace (
659 EfiGcdAllocateMaxAddressSearchTopDown,
660 EfiGcdMemoryTypeMemoryMappedIo,
661 BitsOfAlignment,
662 AddrLen,
663 &BaseAddress,
664 mDriverImageHandle,
665 NULL
666 );
667
668 if (!EFI_ERROR (Status)) {
669 // We were able to allocate the PCI memory
670 RootBridgeInstance->ResAllocNode[Index].Base = (UINTN)BaseAddress;
671 RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated;
672
673 } else {
674 // Not able to allocate enough PCI memory
675 ReturnStatus = Status;
676
677 if (Status != EFI_OUT_OF_RESOURCES) {
678 RootBridgeInstance->ResAllocNode[Index].Length = 0;
679 }
680 ASSERT (FALSE);
681 }
682 break;
683
684 case TypePMem32:
685 case TypeMem64:
686 case TypePMem64:
687 ReturnStatus = EFI_ABORTED;
688 break;
689 default:
690 ASSERT (FALSE);
691 break;
692 }; //end switch
693 }
694 }
695
696 List = List->ForwardLink;
697 }
698
699 return ReturnStatus;
700 } else {
701 return EFI_NOT_READY;
702 }
703
704 case EfiPciHostBridgeSetResources:
705 break;
706
707 case EfiPciHostBridgeFreeResources:
708 ReturnStatus = EFI_SUCCESS;
709 List = HostBridgeInstance->Head.ForwardLink;
710 while (List != &HostBridgeInstance->Head) {
711 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
712 for (Index = TypeIo; Index < TypeBus; Index++) {
713 if (RootBridgeInstance->ResAllocNode[Index].Status == ResAllocated) {
714 AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
715 BaseAddress = RootBridgeInstance->ResAllocNode[Index].Base;
716 switch (Index) {
717
718 case TypeIo:
719 Status = gDS->FreeIoSpace (BaseAddress, AddrLen);
720 if (EFI_ERROR (Status)) {
721 ReturnStatus = Status;
722 }
723 break;
724
725 case TypeMem32:
726 Status = gDS->FreeMemorySpace (BaseAddress, AddrLen);
727 if (EFI_ERROR (Status)) {
728 ReturnStatus = Status;
729 }
730 break;
731
732 case TypePMem32:
733 break;
734
735 case TypeMem64:
736 break;
737
738 case TypePMem64:
739 break;
740
741 default:
742 ASSERT (FALSE);
743 break;
744
745 }; //end switch
746 RootBridgeInstance->ResAllocNode[Index].Type = Index;
747 RootBridgeInstance->ResAllocNode[Index].Base = 0;
748 RootBridgeInstance->ResAllocNode[Index].Length = 0;
749 RootBridgeInstance->ResAllocNode[Index].Status = ResNone;
750 }
751 }
752
753 List = List->ForwardLink;
754 }
755
756 HostBridgeInstance->ResourceSubmited = FALSE;
757 HostBridgeInstance->CanRestarted = TRUE;
758 return ReturnStatus;
759
760 case EfiPciHostBridgeEndResourceAllocation:
761 HostBridgeInstance->CanRestarted = FALSE;
762 break;
763
764 default:
765 return EFI_INVALID_PARAMETER;
766 }
767
768 return EFI_SUCCESS;
769 }
770
771 /**
772 Return the device handle of the next PCI root bridge that is associated with this Host Bridge.
773
774 This function is called multiple times to retrieve the device handles of all the PCI root bridges that
775 are associated with this PCI host bridge. Each PCI host bridge is associated with one or more PCI
776 root bridges. On each call, the handle that was returned by the previous call is passed into the
777 interface, and on output the interface returns the device handle of the next PCI root bridge. The
778 caller can use the handle to obtain the instance of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
779 for that root bridge. When there are no more PCI root bridges to report, the interface returns
780 EFI_NOT_FOUND. A PCI enumerator must enumerate the PCI root bridges in the order that they
781 are returned by this function.
782 For D945 implementation, there is only one root bridge in PCI host bridge.
783
784 @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
785 @param[in, out] RootBridgeHandle Returns the device handle of the next PCI root bridge.
786
787 @retval EFI_SUCCESS If parameter RootBridgeHandle = NULL, then return the first Rootbridge handle of the
788 specific Host bridge and return EFI_SUCCESS.
789 @retval EFI_NOT_FOUND Can not find the any more root bridge in specific host bridge.
790 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was
791 returned on a previous call to GetNextRootBridge().
792 **/
793 EFI_STATUS
794 EFIAPI
795 GetNextRootBridge(
796 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
797 IN OUT EFI_HANDLE *RootBridgeHandle
798 )
799 {
800 BOOLEAN NoRootBridge;
801 LIST_ENTRY *List;
802 PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
803 PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
804
805 NoRootBridge = TRUE;
806 HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
807 List = HostBridgeInstance->Head.ForwardLink;
808
809
810 while (List != &HostBridgeInstance->Head) {
811 NoRootBridge = FALSE;
812 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
813 if (*RootBridgeHandle == NULL) {
814 //
815 // Return the first Root Bridge Handle of the Host Bridge
816 //
817 *RootBridgeHandle = RootBridgeInstance->Handle;
818 return EFI_SUCCESS;
819 } else {
820 if (*RootBridgeHandle == RootBridgeInstance->Handle) {
821 //
822 // Get next if have
823 //
824 List = List->ForwardLink;
825 if (List!=&HostBridgeInstance->Head) {
826 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
827 *RootBridgeHandle = RootBridgeInstance->Handle;
828 return EFI_SUCCESS;
829 } else {
830 return EFI_NOT_FOUND;
831 }
832 }
833 }
834
835 List = List->ForwardLink;
836 } //end while
837
838 if (NoRootBridge) {
839 return EFI_NOT_FOUND;
840 } else {
841 return EFI_INVALID_PARAMETER;
842 }
843 }
844
845 /**
846 Returns the allocation attributes of a PCI root bridge.
847
848 The function returns the allocation attributes of a specific PCI root bridge. The attributes can vary
849 from one PCI root bridge to another. These attributes are different from the decode-related
850 attributes that are returned by the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The
851 RootBridgeHandle parameter is used to specify the instance of the PCI root bridge. The device
852 handles of all the root bridges that are associated with this host bridge must be obtained by calling
853 GetNextRootBridge(). The attributes are static in the sense that they do not change during or
854 after the enumeration process. The hardware may provide mechanisms to change the attributes on
855 the fly, but such changes must be completed before EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is
856 installed. The permitted values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in
857 "Related Definitions" below. The caller uses these attributes to combine multiple resource requests.
858 For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI bus enumerator needs to
859 include requests for the prefetchable memory in the nonprefetchable memory pool and not request any
860 prefetchable memory.
861 Attribute Description
862 ------------------------------------ ----------------------------------------------------------------------
863 EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM If this bit is set, then the PCI root bridge does not support separate
864 windows for nonprefetchable and prefetchable memory. A PCI bus
865 driver needs to include requests for prefetchable memory in the
866 nonprefetchable memory pool.
867
868 EFI_PCI_HOST_BRIDGE_MEM64_DECODE If this bit is set, then the PCI root bridge supports 64-bit memory
869 windows. If this bit is not set, the PCI bus driver needs to include
870 requests for a 64-bit memory address in the corresponding 32-bit
871 memory pool.
872
873 @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
874 @param[in] RootBridgeHandle The device handle of the PCI root bridge in which the caller is interested. Type
875 EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.
876 @param[out] Attributes The pointer to attribte of root bridge, it is output parameter
877
878 @retval EFI_INVALID_PARAMETER Attribute pointer is NULL
879 @retval EFI_INVALID_PARAMETER RootBridgehandle is invalid.
880 @retval EFI_SUCCESS Success to get attribute of interested root bridge.
881
882 **/
883 EFI_STATUS
884 EFIAPI
885 GetAttributes(
886 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
887 IN EFI_HANDLE RootBridgeHandle,
888 OUT UINT64 *Attributes
889 )
890 {
891 LIST_ENTRY *List;
892 PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
893 PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
894
895 if (Attributes == NULL) {
896 return EFI_INVALID_PARAMETER;
897 }
898
899 HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
900 List = HostBridgeInstance->Head.ForwardLink;
901
902 while (List != &HostBridgeInstance->Head) {
903 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
904 if (RootBridgeHandle == RootBridgeInstance->Handle) {
905 *Attributes = RootBridgeInstance->RootBridgeAttrib;
906 return EFI_SUCCESS;
907 }
908 List = List->ForwardLink;
909 }
910
911 //
912 // RootBridgeHandle is not an EFI_HANDLE
913 // that was returned on a previous call to GetNextRootBridge()
914 //
915 return EFI_INVALID_PARAMETER;
916 }
917
918 /**
919 Sets up the specified PCI root bridge for the bus enumeration process.
920
921 This member function sets up the root bridge for bus enumeration and returns the PCI bus range
922 over which the search should be performed in ACPI 2.0 resource descriptor format.
923
924 @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.
925 @param[in] RootBridgeHandle The PCI Root Bridge to be set up.
926 @param[out] Configuration Pointer to the pointer to the PCI bus resource descriptor.
927
928 @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle
929 @retval EFI_OUT_OF_RESOURCES Fail to allocate ACPI resource descriptor tag.
930 @retval EFI_SUCCESS Sucess to allocate ACPI resource descriptor.
931
932 **/
933 EFI_STATUS
934 EFIAPI
935 StartBusEnumeration(
936 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
937 IN EFI_HANDLE RootBridgeHandle,
938 OUT VOID **Configuration
939 )
940 {
941 LIST_ENTRY *List;
942 PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
943 PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
944 VOID *Buffer;
945 UINT8 *Temp;
946 UINT64 BusStart;
947 UINT64 BusEnd;
948
949 HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
950 List = HostBridgeInstance->Head.ForwardLink;
951
952 while (List != &HostBridgeInstance->Head) {
953 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
954 if (RootBridgeHandle == RootBridgeInstance->Handle) {
955 //
956 // Set up the Root Bridge for Bus Enumeration
957 //
958 BusStart = RootBridgeInstance->BusBase;
959 BusEnd = RootBridgeInstance->BusLimit;
960 //
961 // Program the Hardware(if needed) if error return EFI_DEVICE_ERROR
962 //
963
964 Buffer = AllocatePool (sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof(EFI_ACPI_END_TAG_DESCRIPTOR));
965 if (Buffer == NULL) {
966 return EFI_OUT_OF_RESOURCES;
967 }
968
969 Temp = (UINT8 *)Buffer;
970
971 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Desc = 0x8A;
972 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Len = 0x2B;
973 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->ResType = 2;
974 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->GenFlag = 0;
975 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->SpecificFlag = 0;
976 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrSpaceGranularity = 0;
977 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMin = BusStart;
978 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMax = 0;
979 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrTranslationOffset = 0;
980 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrLen = BusEnd - BusStart + 1;
981
982 Temp = Temp + sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
983 ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79;
984 ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum = 0x0;
985
986 *Configuration = Buffer;
987 return EFI_SUCCESS;
988 }
989 List = List->ForwardLink;
990 }
991
992 return EFI_INVALID_PARAMETER;
993 }
994
995 /**
996 Programs the PCI root bridge hardware so that it decodes the specified PCI bus range.
997
998 This member function programs the specified PCI root bridge to decode the bus range that is
999 specified by the input parameter Configuration.
1000 The bus range information is specified in terms of the ACPI 2.0 resource descriptor format.
1001
1002 @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance
1003 @param[in] RootBridgeHandle The PCI Root Bridge whose bus range is to be programmed
1004 @param[in] Configuration The pointer to the PCI bus resource descriptor
1005
1006 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
1007 @retval EFI_INVALID_PARAMETER Configuration is NULL.
1008 @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.
1009 @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI 2.0 bus resource descriptor.
1010 @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 resource descriptors other than
1011 bus descriptors.
1012 @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid ACPI resource descriptors.
1013 @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for this root bridge.
1014 @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this root bridge.
1015 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.
1016 @retval EFI_SUCCESS The bus range for the PCI root bridge was programmed.
1017
1018 **/
1019 EFI_STATUS
1020 EFIAPI
1021 SetBusNumbers(
1022 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
1023 IN EFI_HANDLE RootBridgeHandle,
1024 IN VOID *Configuration
1025 )
1026 {
1027 LIST_ENTRY *List;
1028 PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
1029 PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
1030 UINT8 *Ptr;
1031 UINTN BusStart;
1032 UINTN BusEnd;
1033 UINTN BusLen;
1034
1035 if (Configuration == NULL) {
1036 return EFI_INVALID_PARAMETER;
1037 }
1038
1039 Ptr = Configuration;
1040
1041 //
1042 // Check the Configuration is valid
1043 //
1044 if(*Ptr != ACPI_ADDRESS_SPACE_DESCRIPTOR) {
1045 return EFI_INVALID_PARAMETER;
1046 }
1047
1048 if (((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->ResType != 2) {
1049 return EFI_INVALID_PARAMETER;
1050 }
1051
1052 Ptr += sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
1053 if (*Ptr != ACPI_END_TAG_DESCRIPTOR) {
1054 return EFI_INVALID_PARAMETER;
1055 }
1056
1057 HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
1058 List = HostBridgeInstance->Head.ForwardLink;
1059
1060 Ptr = Configuration;
1061
1062 while (List != &HostBridgeInstance->Head) {
1063 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
1064 if (RootBridgeHandle == RootBridgeInstance->Handle) {
1065 BusStart = (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrRangeMin;
1066 BusLen = (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrLen;
1067 BusEnd = BusStart + BusLen - 1;
1068
1069 if (BusStart > BusEnd) {
1070 return EFI_INVALID_PARAMETER;
1071 }
1072
1073 if ((BusStart < RootBridgeInstance->BusBase) || (BusEnd > RootBridgeInstance->BusLimit)) {
1074 return EFI_INVALID_PARAMETER;
1075 }
1076
1077 //
1078 // Update the Bus Range
1079 //
1080 RootBridgeInstance->ResAllocNode[TypeBus].Base = BusStart;
1081 RootBridgeInstance->ResAllocNode[TypeBus].Length = BusLen;
1082 RootBridgeInstance->ResAllocNode[TypeBus].Status = ResAllocated;
1083
1084 //
1085 // Program the Root Bridge Hardware
1086 //
1087
1088 return EFI_SUCCESS;
1089 }
1090
1091 List = List->ForwardLink;
1092 }
1093
1094 return EFI_INVALID_PARAMETER;
1095 }
1096
1097
1098 /**
1099 Submits the I/O and memory resource requirements for the specified PCI root bridge.
1100
1101 This function is used to submit all the I/O and memory resources that are required by the specified
1102 PCI root bridge. The input parameter Configuration is used to specify the following:
1103 - The various types of resources that are required
1104 - The associated lengths in terms of ACPI 2.0 resource descriptor format
1105
1106 @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
1107 @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory resource requirements are being submitted.
1108 @param[in] Configuration The pointer to the PCI I/O and PCI memory resource descriptor.
1109
1110 @retval EFI_SUCCESS The I/O and memory resource requests for a PCI root bridge were accepted.
1111 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
1112 @retval EFI_INVALID_PARAMETER Configuration is NULL.
1113 @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.
1114 @retval EFI_INVALID_PARAMETER Configuration includes requests for one or more resource types that are
1115 not supported by this PCI root bridge. This error will happen if the caller
1116 did not combine resources according to Attributes that were returned by
1117 GetAllocAttributes().
1118 @retval EFI_INVALID_PARAMETER Address Range Maximum" is invalid.
1119 @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this PCI root bridge.
1120 @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for this PCI root bridge.
1121
1122 **/
1123 EFI_STATUS
1124 EFIAPI
1125 SubmitResources(
1126 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
1127 IN EFI_HANDLE RootBridgeHandle,
1128 IN VOID *Configuration
1129 )
1130 {
1131 LIST_ENTRY *List;
1132 PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
1133 PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
1134 UINT8 *Temp;
1135 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
1136 UINT64 AddrLen;
1137 UINT64 Alignment;
1138
1139 //
1140 // Check the input parameter: Configuration
1141 //
1142 if (Configuration == NULL) {
1143 return EFI_INVALID_PARAMETER;
1144 }
1145
1146 HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
1147 List = HostBridgeInstance->Head.ForwardLink;
1148
1149 Temp = (UINT8 *)Configuration;
1150 while ( *Temp == 0x8A) {
1151 Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) ;
1152 }
1153 if (*Temp != 0x79) {
1154 return EFI_INVALID_PARAMETER;
1155 }
1156
1157 Temp = (UINT8 *)Configuration;
1158 while (List != &HostBridgeInstance->Head) {
1159 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
1160 if (RootBridgeHandle == RootBridgeInstance->Handle) {
1161 for (;
1162 *Temp == 0x8A;
1163 Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR)
1164 ) {
1165 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;
1166
1167 //
1168 // Check Address Length
1169 //
1170 if (Ptr->AddrLen == 0) {
1171 HostBridgeInstance->ResourceSubmited = TRUE;
1172 continue;
1173 }
1174 if (Ptr->AddrLen > 0xffffffff) {
1175 return EFI_INVALID_PARAMETER;
1176 }
1177
1178 //
1179 // Check address range alignment
1180 //
1181 if (Ptr->AddrRangeMax >= 0xffffffff || Ptr->AddrRangeMax != (GetPowerOfTwo64 (Ptr->AddrRangeMax + 1) - 1)) {
1182 return EFI_INVALID_PARAMETER;
1183 }
1184
1185 switch (Ptr->ResType) {
1186
1187 case 0:
1188
1189 //
1190 // Check invalid Address Sapce Granularity
1191 //
1192 if (Ptr->AddrSpaceGranularity != 32) {
1193 return EFI_INVALID_PARAMETER;
1194 }
1195
1196 //
1197 // check the memory resource request is supported by PCI root bridge
1198 //
1199 if (RootBridgeInstance->RootBridgeAttrib == EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM &&
1200 Ptr->SpecificFlag == 0x06) {
1201 return EFI_INVALID_PARAMETER;
1202 }
1203
1204 AddrLen = Ptr->AddrLen;
1205 Alignment = Ptr->AddrRangeMax;
1206 if (Ptr->AddrSpaceGranularity == 32) {
1207 if (Ptr->SpecificFlag == 0x06) {
1208 //
1209 // Apply from GCD
1210 //
1211 RootBridgeInstance->ResAllocNode[TypePMem32].Status = ResSubmitted;
1212 } else {
1213 RootBridgeInstance->ResAllocNode[TypeMem32].Length = AddrLen;
1214 RootBridgeInstance->ResAllocNode[TypeMem32].Alignment = Alignment;
1215 RootBridgeInstance->ResAllocNode[TypeMem32].Status = ResRequested;
1216 HostBridgeInstance->ResourceSubmited = TRUE;
1217 }
1218 }
1219
1220 if (Ptr->AddrSpaceGranularity == 64) {
1221 if (Ptr->SpecificFlag == 0x06) {
1222 RootBridgeInstance->ResAllocNode[TypePMem64].Status = ResSubmitted;
1223 } else {
1224 RootBridgeInstance->ResAllocNode[TypeMem64].Status = ResSubmitted;
1225 }
1226 }
1227 break;
1228
1229 case 1:
1230 AddrLen = (UINTN) Ptr->AddrLen;
1231 Alignment = (UINTN) Ptr->AddrRangeMax;
1232 RootBridgeInstance->ResAllocNode[TypeIo].Length = AddrLen;
1233 RootBridgeInstance->ResAllocNode[TypeIo].Alignment = Alignment;
1234 RootBridgeInstance->ResAllocNode[TypeIo].Status = ResRequested;
1235 HostBridgeInstance->ResourceSubmited = TRUE;
1236 break;
1237
1238 default:
1239 break;
1240 };
1241 }
1242
1243 return EFI_SUCCESS;
1244 }
1245
1246 List = List->ForwardLink;
1247 }
1248
1249 return EFI_INVALID_PARAMETER;
1250 }
1251
1252 /**
1253 Returns the proposed resource settings for the specified PCI root bridge.
1254
1255 This member function returns the proposed resource settings for the specified PCI root bridge. The
1256 proposed resource settings are prepared when NotifyPhase() is called with a Phase of
1257 EfiPciHostBridgeAllocateResources. The output parameter Configuration
1258 specifies the following:
1259 - The various types of resources, excluding bus resources, that are allocated
1260 - The associated lengths in terms of ACPI 2.0 resource descriptor format
1261
1262 @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
1263 @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.
1264 @param[out] Configuration The pointer to the pointer to the PCI I/O and memory resource descriptor.
1265
1266 @retval EFI_SUCCESS The requested parameters were returned.
1267 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
1268 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.
1269 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1270
1271 **/
1272 EFI_STATUS
1273 EFIAPI
1274 GetProposedResources(
1275 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
1276 IN EFI_HANDLE RootBridgeHandle,
1277 OUT VOID **Configuration
1278 )
1279 {
1280 LIST_ENTRY *List;
1281 PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
1282 PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
1283 UINTN Index;
1284 UINTN Number;
1285 VOID *Buffer;
1286 UINT8 *Temp;
1287 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
1288 UINT64 ResStatus;
1289
1290 Buffer = NULL;
1291 Number = 0;
1292 //
1293 // Get the Host Bridge Instance from the resource allocation protocol
1294 //
1295 HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
1296 List = HostBridgeInstance->Head.ForwardLink;
1297
1298 //
1299 // Enumerate the root bridges in this host bridge
1300 //
1301 while (List != &HostBridgeInstance->Head) {
1302 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
1303 if (RootBridgeHandle == RootBridgeInstance->Handle) {
1304 for (Index = 0; Index < TypeBus; Index ++) {
1305 if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {
1306 Number ++;
1307 }
1308 }
1309
1310 if (Number == 0) {
1311 EFI_ACPI_END_TAG_DESCRIPTOR *End;
1312
1313 End = AllocateZeroPool (sizeof *End);
1314 if (End == NULL) {
1315 return EFI_OUT_OF_RESOURCES;
1316 }
1317 End->Desc = ACPI_END_TAG_DESCRIPTOR;
1318 *Configuration = End;
1319 return EFI_SUCCESS;
1320 }
1321
1322 Buffer = AllocateZeroPool (Number * sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof(EFI_ACPI_END_TAG_DESCRIPTOR));
1323 if (Buffer == NULL) {
1324 return EFI_OUT_OF_RESOURCES;
1325 }
1326
1327 Temp = Buffer;
1328 for (Index = 0; Index < TypeBus; Index ++) {
1329 if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {
1330 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;
1331 ResStatus = RootBridgeInstance->ResAllocNode[Index].Status;
1332
1333 switch (Index) {
1334
1335 case TypeIo:
1336 //
1337 // Io
1338 //
1339 Ptr->Desc = 0x8A;
1340 Ptr->Len = 0x2B;
1341 Ptr->ResType = 1;
1342 Ptr->GenFlag = 0;
1343 Ptr->SpecificFlag = 0;
1344 Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;
1345 Ptr->AddrRangeMax = 0;
1346 Ptr->AddrTranslationOffset = \
1347 (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
1348 Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
1349 break;
1350
1351 case TypeMem32:
1352 //
1353 // Memory 32
1354 //
1355 Ptr->Desc = 0x8A;
1356 Ptr->Len = 0x2B;
1357 Ptr->ResType = 0;
1358 Ptr->GenFlag = 0;
1359 Ptr->SpecificFlag = 0;
1360 Ptr->AddrSpaceGranularity = 32;
1361 Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;
1362 Ptr->AddrRangeMax = 0;
1363 Ptr->AddrTranslationOffset = \
1364 (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
1365 Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
1366 break;
1367
1368 case TypePMem32:
1369 //
1370 // Prefetch memory 32
1371 //
1372 Ptr->Desc = 0x8A;
1373 Ptr->Len = 0x2B;
1374 Ptr->ResType = 0;
1375 Ptr->GenFlag = 0;
1376 Ptr->SpecificFlag = 6;
1377 Ptr->AddrSpaceGranularity = 32;
1378 Ptr->AddrRangeMin = 0;
1379 Ptr->AddrRangeMax = 0;
1380 Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;
1381 Ptr->AddrLen = 0;
1382 break;
1383
1384 case TypeMem64:
1385 //
1386 // Memory 64
1387 //
1388 Ptr->Desc = 0x8A;
1389 Ptr->Len = 0x2B;
1390 Ptr->ResType = 0;
1391 Ptr->GenFlag = 0;
1392 Ptr->SpecificFlag = 0;
1393 Ptr->AddrSpaceGranularity = 64;
1394 Ptr->AddrRangeMin = 0;
1395 Ptr->AddrRangeMax = 0;
1396 Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;
1397 Ptr->AddrLen = 0;
1398 break;
1399
1400 case TypePMem64:
1401 //
1402 // Prefetch memory 64
1403 //
1404 Ptr->Desc = 0x8A;
1405 Ptr->Len = 0x2B;
1406 Ptr->ResType = 0;
1407 Ptr->GenFlag = 0;
1408 Ptr->SpecificFlag = 6;
1409 Ptr->AddrSpaceGranularity = 64;
1410 Ptr->AddrRangeMin = 0;
1411 Ptr->AddrRangeMax = 0;
1412 Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;
1413 Ptr->AddrLen = 0;
1414 break;
1415 };
1416
1417 Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
1418 }
1419 }
1420
1421 ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79;
1422 ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum = 0x0;
1423
1424 *Configuration = Buffer;
1425
1426 return EFI_SUCCESS;
1427 }
1428
1429 List = List->ForwardLink;
1430 }
1431
1432 return EFI_INVALID_PARAMETER;
1433 }
1434
1435 /**
1436 Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various
1437 stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual
1438 PCI controllers before enumeration.
1439
1440 This function is called during the PCI enumeration process. No specific action is expected from this
1441 member function. It allows the host bridge driver to preinitialize individual PCI controllers before
1442 enumeration.
1443
1444 @param This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
1445 @param RootBridgeHandle The associated PCI root bridge handle. Type EFI_HANDLE is defined in
1446 InstallProtocolInterface() in the UEFI 2.0 Specification.
1447 @param PciAddress The address of the PCI device on the PCI bus. This address can be passed to the
1448 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functions to access the PCI
1449 configuration space of the device. See Table 12-1 in the UEFI 2.0 Specification for
1450 the definition of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS.
1451 @param Phase The phase of the PCI device enumeration.
1452
1453 @retval EFI_SUCCESS The requested parameters were returned.
1454 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
1455 @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in
1456 EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.
1457 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should
1458 not enumerate this device, including its child devices if it is a PCI-to-PCI
1459 bridge.
1460
1461 **/
1462 EFI_STATUS
1463 EFIAPI
1464 PreprocessController (
1465 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
1466 IN EFI_HANDLE RootBridgeHandle,
1467 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
1468 IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
1469 )
1470 {
1471 PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
1472 PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
1473 LIST_ENTRY *List;
1474
1475 HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
1476 List = HostBridgeInstance->Head.ForwardLink;
1477
1478 //
1479 // Enumerate the root bridges in this host bridge
1480 //
1481 while (List != &HostBridgeInstance->Head) {
1482 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
1483 if (RootBridgeHandle == RootBridgeInstance->Handle) {
1484 break;
1485 }
1486 List = List->ForwardLink;
1487 }
1488 if (List == &HostBridgeInstance->Head) {
1489 return EFI_INVALID_PARAMETER;
1490 }
1491
1492 if ((UINT32)Phase > EfiPciBeforeResourceCollection) {
1493 return EFI_INVALID_PARAMETER;
1494 }
1495
1496 return EFI_SUCCESS;
1497 }
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