2 IA32 and X64 Specific relocation fixups
4 Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
5 Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #include <Common/UefiBaseTypes.h>
17 #include <IndustryStandard/PeImage.h>
18 #include "PeCoffLib.h"
19 #include "CommonLib.h"
20 #include "EfiUtilityMsgs.h"
23 #define EXT_IMM64(Value, Address, Size, InstPos, ValPos) \
24 Value |= (((UINT64)((*(Address) >> InstPos) & (((UINT64)1 << Size) - 1))) << ValPos)
26 #define INS_IMM64(Value, Address, Size, InstPos, ValPos) \
27 *(UINT32*)Address = (*(UINT32*)Address & ~(((1 << Size) - 1) << InstPos)) | \
28 ((UINT32)((((UINT64)Value >> ValPos) & (((UINT64)1 << Size) - 1))) << InstPos)
30 #define IMM64_IMM7B_INST_WORD_X 3
31 #define IMM64_IMM7B_SIZE_X 7
32 #define IMM64_IMM7B_INST_WORD_POS_X 4
33 #define IMM64_IMM7B_VAL_POS_X 0
35 #define IMM64_IMM9D_INST_WORD_X 3
36 #define IMM64_IMM9D_SIZE_X 9
37 #define IMM64_IMM9D_INST_WORD_POS_X 18
38 #define IMM64_IMM9D_VAL_POS_X 7
40 #define IMM64_IMM5C_INST_WORD_X 3
41 #define IMM64_IMM5C_SIZE_X 5
42 #define IMM64_IMM5C_INST_WORD_POS_X 13
43 #define IMM64_IMM5C_VAL_POS_X 16
45 #define IMM64_IC_INST_WORD_X 3
46 #define IMM64_IC_SIZE_X 1
47 #define IMM64_IC_INST_WORD_POS_X 12
48 #define IMM64_IC_VAL_POS_X 21
50 #define IMM64_IMM41a_INST_WORD_X 1
51 #define IMM64_IMM41a_SIZE_X 10
52 #define IMM64_IMM41a_INST_WORD_POS_X 14
53 #define IMM64_IMM41a_VAL_POS_X 22
55 #define IMM64_IMM41b_INST_WORD_X 1
56 #define IMM64_IMM41b_SIZE_X 8
57 #define IMM64_IMM41b_INST_WORD_POS_X 24
58 #define IMM64_IMM41b_VAL_POS_X 32
60 #define IMM64_IMM41c_INST_WORD_X 2
61 #define IMM64_IMM41c_SIZE_X 23
62 #define IMM64_IMM41c_INST_WORD_POS_X 0
63 #define IMM64_IMM41c_VAL_POS_X 40
65 #define IMM64_SIGN_INST_WORD_X 3
66 #define IMM64_SIGN_SIZE_X 1
67 #define IMM64_SIGN_INST_WORD_POS_X 27
68 #define IMM64_SIGN_VAL_POS_X 63
71 PeCoffLoaderRelocateIa32Image (
74 IN OUT CHAR8
**FixupData
,
81 Performs an IA-32 specific relocation fixup
85 Reloc - Pointer to the relocation record
87 Fixup - Pointer to the address to fix up
89 FixupData - Pointer to a buffer to log the fixups
91 Adjust - The offset to adjust the fixup
95 EFI_UNSUPPORTED - Unsupported now
99 return RETURN_UNSUPPORTED
;
104 Pass in a pointer to an ARM MOVT or MOVW immediate instruciton and
105 return the immediate data encoded in the instruction
107 @param Instruction Pointer to ARM MOVT or MOVW immediate instruction
109 @return Immediate address encoded in the instruction
113 ThumbMovtImmediateAddress (
114 IN UINT16
*Instruction
120 // Thumb2 is two 16-bit instructions working together. Not a single 32-bit instruction
121 // Example MOVT R0, #0 is 0x0000f2c0 or 0xf2c0 0x0000
122 Movt
= (*Instruction
<< 16) | (*(Instruction
+ 1));
124 // imm16 = imm4:i:imm3:imm8
125 // imm4 -> Bit19:Bit16
127 // imm3 -> Bit14:Bit12
129 Address
= (UINT16
)(Movt
& 0x000000ff); // imm8
130 Address
|= (UINT16
)((Movt
>> 4) & 0x0000f700); // imm4 imm3
131 Address
|= (((Movt
& BIT26
) != 0) ? BIT11
: 0); // i
137 Update an ARM MOVT or MOVW immediate instruction immediate data.
139 @param Instruction Pointer to ARM MOVT or MOVW immediate instruction
140 @param Address New addres to patch into the instruction
143 ThumbMovtImmediatePatch (
144 IN OUT UINT16
*Instruction
,
150 // First 16-bit chunk of instruciton
151 Patch
= ((Address
>> 12) & 0x000f); // imm4
152 Patch
|= (((Address
& BIT11
) != 0) ? BIT10
: 0); // i
153 *Instruction
= (*Instruction
& ~0x040f) | Patch
;
155 // Second 16-bit chunk of instruction
156 Patch
= Address
& 0x000000ff; // imm8
157 Patch
|= ((Address
<< 4) & 0x00007000); // imm3
159 *Instruction
= (*Instruction
& ~0x70ff) | Patch
;
163 Pass in a pointer to an ARM MOVW/MOVT instruciton pair and
164 return the immediate data encoded in the two` instruction
166 @param Instructions Pointer to ARM MOVW/MOVT insturction pair
168 @return Immediate address encoded in the instructions
173 ThumbMovwMovtImmediateAddress (
174 IN UINT16
*Instructions
180 Word
= Instructions
; // MOVW
181 Top
= Word
+ 2; // MOVT
183 return (ThumbMovtImmediateAddress (Top
) << 16) + ThumbMovtImmediateAddress (Word
);
188 Update an ARM MOVW/MOVT immediate instruction instruction pair.
190 @param Instructions Pointer to ARM MOVW/MOVT instruction pair
191 @param Address New addres to patch into the instructions
195 ThumbMovwMovtImmediatePatch (
196 IN OUT UINT16
*Instructions
,
203 Word
= (UINT16
*)Instructions
; // MOVW
204 Top
= Word
+ 2; // MOVT
206 ThumbMovtImmediatePatch (Word
, (UINT16
)(Address
& 0xffff));
207 ThumbMovtImmediatePatch (Top
, (UINT16
)(Address
>> 16));
212 Performs an ARM-based specific relocation fixup and is a no-op on other
215 @param Reloc Pointer to the relocation record.
216 @param Fixup Pointer to the address to fix up.
217 @param FixupData Pointer to a buffer to log the fixups.
218 @param Adjust The offset to adjust the fixup.
224 PeCoffLoaderRelocateArmImage (
227 IN OUT CHAR8
**FixupData
,
234 Fixup16
= (UINT16
*) Fixup
;
236 switch ((**Reloc
) >> 12) {
238 case EFI_IMAGE_REL_BASED_ARM_MOV32T
:
239 FixupVal
= ThumbMovwMovtImmediateAddress (Fixup16
) + (UINT32
)Adjust
;
240 ThumbMovwMovtImmediatePatch (Fixup16
, FixupVal
);
243 if (*FixupData
!= NULL
) {
244 *FixupData
= ALIGN_POINTER(*FixupData
, sizeof(UINT64
));
245 CopyMem (*FixupData
, Fixup16
, sizeof (UINT64
));
246 *FixupData
= *FixupData
+ sizeof(UINT64
);
250 case EFI_IMAGE_REL_BASED_ARM_MOV32A
:
251 // break omitted - ARM instruction encoding not implemented
253 return RETURN_UNSUPPORTED
;
256 return RETURN_SUCCESS
;