BaseTools/Source/C/Include/IndustryStandard/pci22.h

   1 /** @file
   2   Support for PCI 2.2 standard.
   3
   4   Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
   5
   6   This program and the accompanying materials are licensed and made available
   7   under the terms and conditions of the BSD License which accompanies this
   8   distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef _PCI22_H
  17 #define _PCI22_H
  18
  19 #define PCI_MAX_SEGMENT 0
  20
  21 #define PCI_MAX_BUS     255
  22
  23 #define PCI_MAX_DEVICE  31
  24 #define PCI_MAX_FUNC    7
  25
  26 //
  27 // Command
  28 //
  29 #define PCI_VGA_PALETTE_SNOOP_DISABLED  0x20
  30
  31 #pragma pack(push, 1)
  32 typedef struct {
  33   UINT16  VendorId;
  34   UINT16  DeviceId;
  35   UINT16  Command;
  36   UINT16  Status;
  37   UINT8   RevisionID;
  38   UINT8   ClassCode[3];
  39   UINT8   CacheLineSize;
  40   UINT8   LatencyTimer;
  41   UINT8   HeaderType;
  42   UINT8   BIST;
  43 } PCI_DEVICE_INDEPENDENT_REGION;
  44
  45 typedef struct {
  46   UINT32  Bar[6];
  47   UINT32  CISPtr;
  48   UINT16  SubsystemVendorID;
  49   UINT16  SubsystemID;
  50   UINT32  ExpansionRomBar;
  51   UINT8   CapabilityPtr;
  52   UINT8   Reserved1[3];
  53   UINT32  Reserved2;
  54   UINT8   InterruptLine;
  55   UINT8   InterruptPin;
  56   UINT8   MinGnt;
  57   UINT8   MaxLat;
  58 } PCI_DEVICE_HEADER_TYPE_REGION;
  59
  60 typedef struct {
  61   PCI_DEVICE_INDEPENDENT_REGION Hdr;
  62   PCI_DEVICE_HEADER_TYPE_REGION Device;
  63 } PCI_TYPE00;
  64
  65 typedef struct {
  66   UINT32  Bar[2];
  67   UINT8   PrimaryBus;
  68   UINT8   SecondaryBus;
  69   UINT8   SubordinateBus;
  70   UINT8   SecondaryLatencyTimer;
  71   UINT8   IoBase;
  72   UINT8   IoLimit;
  73   UINT16  SecondaryStatus;
  74   UINT16  MemoryBase;
  75   UINT16  MemoryLimit;
  76   UINT16  PrefetchableMemoryBase;
  77   UINT16  PrefetchableMemoryLimit;
  78   UINT32  PrefetchableBaseUpper32;
  79   UINT32  PrefetchableLimitUpper32;
  80   UINT16  IoBaseUpper16;
  81   UINT16  IoLimitUpper16;
  82   UINT8   CapabilityPtr;
  83   UINT8   Reserved[3];
  84   UINT32  ExpansionRomBAR;
  85   UINT8   InterruptLine;
  86   UINT8   InterruptPin;
  87   UINT16  BridgeControl;
  88 } PCI_BRIDGE_CONTROL_REGISTER;
  89
  90 typedef struct {
  91   PCI_DEVICE_INDEPENDENT_REGION Hdr;
  92   PCI_BRIDGE_CONTROL_REGISTER   Bridge;
  93 } PCI_TYPE01;
  94
  95 typedef union {
  96   PCI_TYPE00  Device;
  97   PCI_TYPE01  Bridge;
  98 } PCI_TYPE_GENERIC;
  99
 100 typedef struct {
 101   UINT32  CardBusSocketReg; // Cardus Socket/ExCA Base
 102   // Address Register
 103   //
 104   UINT16  Reserved;
 105   UINT16  SecondaryStatus;      // Secondary Status
 106   UINT8   PciBusNumber;         // PCI Bus Number
 107   UINT8   CardBusBusNumber;     // CardBus Bus Number
 108   UINT8   SubordinateBusNumber; // Subordinate Bus Number
 109   UINT8   CardBusLatencyTimer;  // CardBus Latency Timer
 110   UINT32  MemoryBase0;          // Memory Base Register 0
 111   UINT32  MemoryLimit0;         // Memory Limit Register 0
 112   UINT32  MemoryBase1;
 113   UINT32  MemoryLimit1;
 114   UINT32  IoBase0;
 115   UINT32  IoLimit0;             // I/O Base Register 0
 116   UINT32  IoBase1;              // I/O Limit Register 0
 117   UINT32  IoLimit1;
 118   UINT8   InterruptLine;        // Interrupt Line
 119   UINT8   InterruptPin;         // Interrupt Pin
 120   UINT16  BridgeControl;        // Bridge Control
 121 } PCI_CARDBUS_CONTROL_REGISTER;
 122
 123 //
 124 // Definitions of PCI class bytes and manipulation macros.
 125 //
 126 #define PCI_CLASS_OLD                 0x00
 127 #define PCI_CLASS_OLD_OTHER           0x00
 128 #define PCI_CLASS_OLD_VGA             0x01
 129
 130 #define PCI_CLASS_MASS_STORAGE        0x01
 131 #define PCI_CLASS_MASS_STORAGE_SCSI   0x00
 132 #define PCI_CLASS_MASS_STORAGE_IDE    0x01  // obsolete
 133 #define PCI_CLASS_IDE                 0x01
 134 #define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
 135 #define PCI_CLASS_MASS_STORAGE_IPI    0x03
 136 #define PCI_CLASS_MASS_STORAGE_RAID   0x04
 137 #define PCI_CLASS_MASS_STORAGE_OTHER  0x80
 138
 139 #define PCI_CLASS_NETWORK             0x02
 140 #define PCI_CLASS_NETWORK_ETHERNET    0x00
 141 #define PCI_CLASS_ETHERNET            0x00  // obsolete
 142 #define PCI_CLASS_NETWORK_TOKENRING   0x01
 143 #define PCI_CLASS_NETWORK_FDDI        0x02
 144 #define PCI_CLASS_NETWORK_ATM         0x03
 145 #define PCI_CLASS_NETWORK_ISDN        0x04
 146 #define PCI_CLASS_NETWORK_OTHER       0x80
 147
 148 #define PCI_CLASS_DISPLAY             0x03
 149 #define PCI_CLASS_DISPLAY_CTRL        0x03  // obsolete
 150 #define PCI_CLASS_DISPLAY_VGA         0x00
 151 #define PCI_CLASS_VGA                 0x00  // obsolete
 152 #define PCI_CLASS_DISPLAY_XGA         0x01
 153 #define PCI_CLASS_DISPLAY_3D          0x02
 154 #define PCI_CLASS_DISPLAY_OTHER       0x80
 155 #define PCI_CLASS_DISPLAY_GFX         0x80
 156 #define PCI_CLASS_GFX                 0x80  // obsolete
 157 #define PCI_CLASS_BRIDGE              0x06
 158 #define PCI_CLASS_BRIDGE_HOST         0x00
 159 #define PCI_CLASS_BRIDGE_ISA          0x01
 160 #define PCI_CLASS_ISA                 0x01  // obsolete
 161 #define PCI_CLASS_BRIDGE_EISA         0x02
 162 #define PCI_CLASS_BRIDGE_MCA          0x03
 163 #define PCI_CLASS_BRIDGE_P2P          0x04
 164 #define PCI_CLASS_BRIDGE_PCMCIA       0x05
 165 #define PCI_CLASS_BRIDGE_NUBUS        0x06
 166 #define PCI_CLASS_BRIDGE_CARDBUS      0x07
 167 #define PCI_CLASS_BRIDGE_RACEWAY      0x08
 168 #define PCI_CLASS_BRIDGE_ISA_PDECODE  0x80
 169 #define PCI_CLASS_ISA_POSITIVE_DECODE 0x80  // obsolete
 170
 171 #define PCI_CLASS_SCC                 0x07  // Simple communications controllers
 172 #define PCI_SUBCLASS_SERIAL           0x00
 173 #define PCI_IF_GENERIC_XT             0x00
 174 #define PCI_IF_16450                  0x01
 175 #define PCI_IF_16550                  0x02
 176 #define PCI_IF_16650                  0x03
 177 #define PCI_IF_16750                  0x04
 178 #define PCI_IF_16850                  0x05
 179 #define PCI_IF_16950                  0x06
 180 #define PCI_SUBCLASS_PARALLEL         0x01
 181 #define PCI_IF_PARALLEL_PORT          0x00
 182 #define PCI_IF_BI_DIR_PARALLEL_PORT   0x01
 183 #define PCI_IF_ECP_PARALLEL_PORT      0x02
 184 #define PCI_IF_1284_CONTROLLER        0x03
 185 #define PCI_IF_1284_DEVICE            0xFE
 186 #define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
 187 #define PCI_SUBCLASS_MODEM            0x03
 188 #define PCI_IF_GENERIC_MODEM          0x00
 189 #define PCI_IF_16450_MODEM            0x01
 190 #define PCI_IF_16550_MODEM            0x02
 191 #define PCI_IF_16650_MODEM            0x03
 192 #define PCI_IF_16750_MODEM            0x04
 193 #define PCI_SUBCLASS_OTHER            0x80
 194
 195 #define PCI_CLASS_SYSTEM_PERIPHERAL   0x08
 196 #define PCI_SUBCLASS_PIC              0x00
 197 #define PCI_IF_8259_PIC               0x00
 198 #define PCI_IF_ISA_PIC                0x01
 199 #define PCI_IF_EISA_PIC               0x02
 200 #define PCI_IF_APIC_CONTROLLER        0x10 // I/O APIC interrupt controller , 32 bye none-prefectable memory.
 201 #define PCI_IF_APIC_CONTROLLER2       0x20
 202 #define PCI_SUBCLASS_TIMER            0x02
 203 #define PCI_IF_8254_TIMER             0x00
 204 #define PCI_IF_ISA_TIMER              0x01
 205 #define PCI_EISA_TIMER                0x02
 206 #define PCI_SUBCLASS_RTC              0x03
 207 #define PCI_IF_GENERIC_RTC            0x00
 208 #define PCI_IF_ISA_RTC                0x00
 209 #define PCI_SUBCLASS_PNP_CONTROLLER   0x04 // HotPlug Controller
 210
 211 #define PCI_CLASS_INPUT_DEVICE        0x09
 212 #define PCI_SUBCLASS_KEYBOARD         0x00
 213 #define PCI_SUBCLASS_PEN              0x01
 214 #define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
 215 #define PCI_SUBCLASS_SCAN_CONTROLLER  0x03
 216 #define PCI_SUBCLASS_GAMEPORT         0x04
 217
 218 #define PCI_CLASS_DOCKING_STATION     0x0A
 219
 220 #define PCI_CLASS_PROCESSOR           0x0B
 221 #define PCI_SUBCLASS_PROC_386         0x00
 222 #define PCI_SUBCLASS_PROC_486         0x01
 223 #define PCI_SUBCLASS_PROC_PENTIUM     0x02
 224 #define PCI_SUBCLASS_PROC_ALPHA       0x10
 225 #define PCI_SUBCLASS_PROC_POWERPC     0x20
 226 #define PCI_SUBCLASS_PROC_MIPS        0x30
 227 #define PCI_SUBCLASS_PROC_CO_PORC     0x40 // Co-Processor
 228
 229 #define PCI_CLASS_SERIAL              0x0C
 230 #define PCI_CLASS_SERIAL_FIREWIRE     0x00
 231 #define PCI_CLASS_SERIAL_ACCESS_BUS   0x01
 232 #define PCI_CLASS_SERIAL_SSA          0x02
 233 #define PCI_CLASS_SERIAL_USB          0x03
 234 #define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
 235 #define PCI_CLASS_SERIAL_SMB          0x05
 236
 237 #define PCI_CLASS_WIRELESS            0x0D
 238 #define PCI_SUBCLASS_IRDA             0x00
 239 #define PCI_SUBCLASS_IR               0x01
 240 #define PCI_SUBCLASS_RF               0x02
 241
 242 #define PCI_CLASS_INTELLIGENT_IO      0x0E
 243
 244 #define PCI_CLASS_SATELLITE           0x0F
 245 #define PCI_SUBCLASS_TV               0x01
 246 #define PCI_SUBCLASS_AUDIO            0x02
 247 #define PCI_SUBCLASS_VOICE            0x03
 248 #define PCI_SUBCLASS_DATA             0x04
 249
 250 #define PCI_SECURITY_CONTROLLER       0x10 // Encryption and decryption controller
 251 #define PCI_SUBCLASS_NET_COMPUT       0x00
 252 #define PCI_SUBCLASS_ENTERTAINMENT    0x10
 253
 254 #define PCI_CLASS_DPIO                0x11
 255
 256 #define IS_CLASS1(_p, c)              ((_p)->Hdr.ClassCode[2] == (c))
 257 #define IS_CLASS2(_p, c, s)           (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
 258 #define IS_CLASS3(_p, c, s, p)        (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
 259
 260 #define IS_PCI_DISPLAY(_p)            IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
 261 #define IS_PCI_VGA(_p)                IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 0)
 262 #define IS_PCI_8514(_p)               IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 1)
 263 #define IS_PCI_GFX(_p)                IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_GFX, 0)
 264 #define IS_PCI_OLD(_p)                IS_CLASS1 (_p, PCI_CLASS_OLD)
 265 #define IS_PCI_OLD_VGA(_p)            IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
 266 #define IS_PCI_IDE(_p)                IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
 267 #define IS_PCI_SCSI(_p)               IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI, 0)
 268 #define IS_PCI_RAID(_p)               IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID, 0)
 269 #define IS_PCI_LPC(_p)                IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA, 0)
 270 #define IS_PCI_P2P(_p)                IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 0)
 271 #define IS_PCI_P2P_SUB(_p)            IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 1)
 272 #define IS_PCI_USB(_p)                IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
 273
 274 #define HEADER_TYPE_DEVICE            0x00
 275 #define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
 276 #define HEADER_TYPE_CARDBUS_BRIDGE    0x02
 277
 278 #define HEADER_TYPE_MULTI_FUNCTION    0x80
 279 #define HEADER_LAYOUT_CODE            0x7f
 280
 281 #define IS_PCI_BRIDGE(_p)             (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
 282 #define IS_CARDBUS_BRIDGE(_p)         (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
 283 #define IS_PCI_MULTI_FUNC(_p)         ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
 284
 285 #define PCI_DEVICE_ROMBAR             0x30
 286 #define PCI_BRIDGE_ROMBAR             0x38
 287
 288 #define PCI_MAX_BAR                   0x0006
 289 #define PCI_MAX_CONFIG_OFFSET         0x0100
 290
 291 #define PCI_VENDOR_ID_OFFSET                        0x00
 292 #define PCI_DEVICE_ID_OFFSET                        0x02
 293 #define PCI_COMMAND_OFFSET                          0x04
 294 #define PCI_PRIMARY_STATUS_OFFSET                   0x06
 295 #define PCI_REVISION_ID_OFFSET                      0x08
 296 #define PCI_CLASSCODE_OFFSET                        0x09
 297 #define PCI_CACHELINE_SIZE_OFFSET                   0x0C
 298 #define PCI_LATENCY_TIMER_OFFSET                    0x0D
 299 #define PCI_HEADER_TYPE_OFFSET                      0x0E
 300 #define PCI_BIST_OFFSET                             0x0F
 301 #define PCI_BASE_ADDRESSREG_OFFSET                  0x10
 302 #define PCI_CARDBUS_CIS_OFFSET                      0x28
 303 #define PCI_SVID_OFFSET                             0x2C // SubSystem Vendor id
 304 #define PCI_SUBSYSTEM_VENDOR_ID_OFFSET              0x2C
 305 #define PCI_SID_OFFSET                              0x2E // SubSystem ID
 306 #define PCI_SUBSYSTEM_ID_OFFSET                     0x2E
 307 #define PCI_EXPANSION_ROM_BASE                      0x30
 308 #define PCI_CAPBILITY_POINTER_OFFSET                0x34
 309 #define PCI_INT_LINE_OFFSET                         0x3C // Interrupt Line Register
 310 #define PCI_INT_PIN_OFFSET                          0x3D // Interrupt Pin Register
 311 #define PCI_MAXGNT_OFFSET                           0x3E // Max Grant Register
 312 #define PCI_MAXLAT_OFFSET                           0x3F // Max Latency Register
 313
 314 #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET          0x3E
 315 #define PCI_BRIDGE_STATUS_REGISTER_OFFSET           0x1E
 316
 317 #define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET      0x18
 318 #define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET    0x19
 319 #define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET  0x1a
 320
 321 typedef union {
 322   struct {
 323     UINT32  Reg : 8;
 324     UINT32  Func : 3;
 325     UINT32  Dev : 5;
 326     UINT32  Bus : 8;
 327     UINT32  Reserved : 7;
 328     UINT32  Enable : 1;
 329   } Bits;
 330   UINT32  Uint32;
 331 } PCI_CONFIG_ACCESS_CF8;
 332
 333 #pragma pack()
 334
 335 #define PCI_EXPANSION_ROM_HEADER_SIGNATURE              0xaa55
 336 #define PCI_DATA_STRUCTURE_SIGNATURE                    SIGNATURE_32 ('P', 'C', 'I', 'R')
 337 #define PCI_CODE_TYPE_PCAT_IMAGE                        0x00
 338 #define PCI_CODE_TYPE_EFI_IMAGE                         0x03
 339 #define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED         0x0001
 340
 341 #define EFI_PCI_COMMAND_IO_SPACE                        0x0001
 342 #define EFI_PCI_COMMAND_MEMORY_SPACE                    0x0002
 343 #define EFI_PCI_COMMAND_BUS_MASTER                      0x0004
 344 #define EFI_PCI_COMMAND_SPECIAL_CYCLE                   0x0008
 345 #define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE     0x0010
 346 #define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP               0x0020
 347 #define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND            0x0040
 348 #define EFI_PCI_COMMAND_STEPPING_CONTROL                0x0080
 349 #define EFI_PCI_COMMAND_SERR                            0x0100
 350 #define EFI_PCI_COMMAND_FAST_BACK_TO_BACK               0x0200
 351
 352 #define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE    0x0001
 353 #define EFI_PCI_BRIDGE_CONTROL_SERR                     0x0002
 354 #define EFI_PCI_BRIDGE_CONTROL_ISA                      0x0004
 355 #define EFI_PCI_BRIDGE_CONTROL_VGA                      0x0008
 356 #define EFI_PCI_BRIDGE_CONTROL_VGA_16                   0x0010
 357 #define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT             0x0020
 358 #define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS      0x0040
 359 #define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK        0x0080
 360 #define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER    0x0100
 361 #define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER  0x0200
 362 #define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS             0x0400
 363 #define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR       0x0800
 364
 365 //
 366 // Following are the PCI-CARDBUS bridge control bit
 367 //
 368 #define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE       0x0080
 369 #define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE   0x0100
 370 #define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE   0x0200
 371 #define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE 0x0400
 372
 373 //
 374 // Following are the PCI status control bit
 375 //
 376 #define EFI_PCI_STATUS_CAPABILITY             0x0010
 377 #define EFI_PCI_STATUS_66MZ_CAPABLE           0x0020
 378 #define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE     0x0080
 379 #define EFI_PCI_MASTER_DATA_PARITY_ERROR      0x0100
 380
 381 #define EFI_PCI_CAPABILITY_PTR                0x34
 382 #define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
 383
 384 #pragma pack(1)
 385 typedef struct {
 386   UINT16  Signature;    // 0xaa55
 387   UINT8   Reserved[0x16];
 388   UINT16  PcirOffset;
 389 } PCI_EXPANSION_ROM_HEADER;
 390
 391 typedef struct {
 392   UINT16  Signature;    // 0xaa55
 393   UINT8   Size512;
 394   UINT8   InitEntryPoint[3];
 395   UINT8   Reserved[0x12];
 396   UINT16  PcirOffset;
 397 } EFI_LEGACY_EXPANSION_ROM_HEADER;
 398
 399 typedef struct {
 400   UINT32  Signature;    // "PCIR"
 401   UINT16  VendorId;
 402   UINT16  DeviceId;
 403   UINT16  Reserved0;
 404   UINT16  Length;
 405   UINT8   Revision;
 406   UINT8   ClassCode[3];
 407   UINT16  ImageLength;
 408   UINT16  CodeRevision;
 409   UINT8   CodeType;
 410   UINT8   Indicator;
 411   UINT16  Reserved1;
 412 } PCI_DATA_STRUCTURE;
 413
 414 //
 415 // PCI Capability List IDs and records
 416 //
 417 #define EFI_PCI_CAPABILITY_ID_PMI     0x01
 418 #define EFI_PCI_CAPABILITY_ID_AGP     0x02
 419 #define EFI_PCI_CAPABILITY_ID_VPD     0x03
 420 #define EFI_PCI_CAPABILITY_ID_SLOTID  0x04
 421 #define EFI_PCI_CAPABILITY_ID_MSI     0x05
 422 #define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
 423 #define EFI_PCI_CAPABILITY_ID_PCIX    0x07
 424
 425 typedef struct {
 426   UINT8 CapabilityID;
 427   UINT8 NextItemPtr;
 428 } EFI_PCI_CAPABILITY_HDR;
 429
 430 //
 431 // Capability EFI_PCI_CAPABILITY_ID_PMI
 432 //
 433 typedef struct {
 434   EFI_PCI_CAPABILITY_HDR  Hdr;
 435   UINT16                  PMC;
 436   UINT16                  PMCSR;
 437   UINT8                   BridgeExtention;
 438   UINT8                   Data;
 439 } EFI_PCI_CAPABILITY_PMI;
 440
 441 //
 442 // Capability EFI_PCI_CAPABILITY_ID_AGP
 443 //
 444 typedef struct {
 445   EFI_PCI_CAPABILITY_HDR  Hdr;
 446   UINT8                   Rev;
 447   UINT8                   Reserved;
 448   UINT32                  Status;
 449   UINT32                  Command;
 450 } EFI_PCI_CAPABILITY_AGP;
 451
 452 //
 453 // Capability EFI_PCI_CAPABILITY_ID_VPD
 454 //
 455 typedef struct {
 456   EFI_PCI_CAPABILITY_HDR  Hdr;
 457   UINT16                  AddrReg;
 458   UINT32                  DataReg;
 459 } EFI_PCI_CAPABILITY_VPD;
 460
 461 //
 462 // Capability EFI_PCI_CAPABILITY_ID_SLOTID
 463 //
 464 typedef struct {
 465   EFI_PCI_CAPABILITY_HDR  Hdr;
 466   UINT8                   ExpnsSlotReg;
 467   UINT8                   ChassisNo;
 468 } EFI_PCI_CAPABILITY_SLOTID;
 469
 470 //
 471 // Capability EFI_PCI_CAPABILITY_ID_MSI
 472 //
 473 typedef struct {
 474   EFI_PCI_CAPABILITY_HDR  Hdr;
 475   UINT16                  MsgCtrlReg;
 476   UINT32                  MsgAddrReg;
 477   UINT16                  MsgDataReg;
 478 } EFI_PCI_CAPABILITY_MSI32;
 479
 480 typedef struct {
 481   EFI_PCI_CAPABILITY_HDR  Hdr;
 482   UINT16                  MsgCtrlReg;
 483   UINT32                  MsgAddrRegLsdw;
 484   UINT32                  MsgAddrRegMsdw;
 485   UINT16                  MsgDataReg;
 486 } EFI_PCI_CAPABILITY_MSI64;
 487
 488 //
 489 // Capability EFI_PCI_CAPABILITY_ID_HOTPLUG
 490 //
 491 typedef struct {
 492   EFI_PCI_CAPABILITY_HDR  Hdr;
 493   //
 494   // not finished - fields need to go here
 495   //
 496 } EFI_PCI_CAPABILITY_HOTPLUG;
 497
 498 //
 499 // Capability EFI_PCI_CAPABILITY_ID_PCIX
 500 //
 501 typedef struct {
 502   EFI_PCI_CAPABILITY_HDR  Hdr;
 503   UINT16                  CommandReg;
 504   UINT32                  StatusReg;
 505 } EFI_PCI_CAPABILITY_PCIX;
 506
 507 typedef struct {
 508   EFI_PCI_CAPABILITY_HDR  Hdr;
 509   UINT16                  SecStatusReg;
 510   UINT32                  StatusReg;
 511   UINT32                  SplitTransCtrlRegUp;
 512   UINT32                  SplitTransCtrlRegDn;
 513 } EFI_PCI_CAPABILITY_PCIX_BRDG;
 514
 515 #define DEVICE_ID_NOCARE    0xFFFF
 516
 517 #define PCI_ACPI_UNUSED     0
 518 #define PCI_BAR_NOCHANGE    0
 519 #define PCI_BAR_OLD_ALIGN   0xFFFFFFFFFFFFFFFFULL
 520 #define PCI_BAR_EVEN_ALIGN  0xFFFFFFFFFFFFFFFEULL
 521 #define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL
 522 #define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL
 523
 524 #define PCI_BAR_IDX0        0x00
 525 #define PCI_BAR_IDX1        0x01
 526 #define PCI_BAR_IDX2        0x02
 527 #define PCI_BAR_IDX3        0x03
 528 #define PCI_BAR_IDX4        0x04
 529 #define PCI_BAR_IDX5        0x05
 530 #define PCI_BAR_ALL         0xFF
 531
 532 #pragma pack(pop)
 533
 534 //
 535 // NOTE: The following header files are included here for
 536 // compatibility consideration.
 537 //
 538 #include "pci23.h"
 539 #include "pci30.h"
 540 #include "EfiPci.h"
 541
 542 #endif