BaseTools/Source/C/Include/IndustryStandard/pci22.h

   1 /** @file
   2   Support for PCI 2.2 standard.
   3
   4   Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
   5
   6   This program and the accompanying materials are licensed and made available
   7   under the terms and conditions of the BSD License which accompanies this
   8   distribution.  The full text of the license may be found at:
   9     http://opensource.org/licenses/bsd-license.php
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14   File Name:  pci22.h
  15
  16 **/
  17
  18 #ifndef _PCI22_H
  19 #define _PCI22_H
  20
  21 #define PCI_MAX_SEGMENT 0
  22
  23 #define PCI_MAX_BUS     255
  24
  25 #define PCI_MAX_DEVICE  31
  26 #define PCI_MAX_FUNC    7
  27
  28 //
  29 // Command
  30 //
  31 #define PCI_VGA_PALETTE_SNOOP_DISABLED  0x20
  32
  33 #pragma pack(push, 1)
  34 typedef struct {
  35   UINT16  VendorId;
  36   UINT16  DeviceId;
  37   UINT16  Command;
  38   UINT16  Status;
  39   UINT8   RevisionID;
  40   UINT8   ClassCode[3];
  41   UINT8   CacheLineSize;
  42   UINT8   LatencyTimer;
  43   UINT8   HeaderType;
  44   UINT8   BIST;
  45 } PCI_DEVICE_INDEPENDENT_REGION;
  46
  47 typedef struct {
  48   UINT32  Bar[6];
  49   UINT32  CISPtr;
  50   UINT16  SubsystemVendorID;
  51   UINT16  SubsystemID;
  52   UINT32  ExpansionRomBar;
  53   UINT8   CapabilityPtr;
  54   UINT8   Reserved1[3];
  55   UINT32  Reserved2;
  56   UINT8   InterruptLine;
  57   UINT8   InterruptPin;
  58   UINT8   MinGnt;
  59   UINT8   MaxLat;
  60 } PCI_DEVICE_HEADER_TYPE_REGION;
  61
  62 typedef struct {
  63   PCI_DEVICE_INDEPENDENT_REGION Hdr;
  64   PCI_DEVICE_HEADER_TYPE_REGION Device;
  65 } PCI_TYPE00;
  66
  67 typedef struct {
  68   UINT32  Bar[2];
  69   UINT8   PrimaryBus;
  70   UINT8   SecondaryBus;
  71   UINT8   SubordinateBus;
  72   UINT8   SecondaryLatencyTimer;
  73   UINT8   IoBase;
  74   UINT8   IoLimit;
  75   UINT16  SecondaryStatus;
  76   UINT16  MemoryBase;
  77   UINT16  MemoryLimit;
  78   UINT16  PrefetchableMemoryBase;
  79   UINT16  PrefetchableMemoryLimit;
  80   UINT32  PrefetchableBaseUpper32;
  81   UINT32  PrefetchableLimitUpper32;
  82   UINT16  IoBaseUpper16;
  83   UINT16  IoLimitUpper16;
  84   UINT8   CapabilityPtr;
  85   UINT8   Reserved[3];
  86   UINT32  ExpansionRomBAR;
  87   UINT8   InterruptLine;
  88   UINT8   InterruptPin;
  89   UINT16  BridgeControl;
  90 } PCI_BRIDGE_CONTROL_REGISTER;
  91
  92 typedef struct {
  93   PCI_DEVICE_INDEPENDENT_REGION Hdr;
  94   PCI_BRIDGE_CONTROL_REGISTER   Bridge;
  95 } PCI_TYPE01;
  96
  97 typedef union {
  98   PCI_TYPE00  Device;
  99   PCI_TYPE01  Bridge;
 100 } PCI_TYPE_GENERIC;
 101
 102 typedef struct {
 103   UINT32  CardBusSocketReg; // Cardus Socket/ExCA Base
 104   // Address Register
 105   //
 106   UINT16  Reserved;
 107   UINT16  SecondaryStatus;      // Secondary Status
 108   UINT8   PciBusNumber;         // PCI Bus Number
 109   UINT8   CardBusBusNumber;     // CardBus Bus Number
 110   UINT8   SubordinateBusNumber; // Subordinate Bus Number
 111   UINT8   CardBusLatencyTimer;  // CardBus Latency Timer
 112   UINT32  MemoryBase0;          // Memory Base Register 0
 113   UINT32  MemoryLimit0;         // Memory Limit Register 0
 114   UINT32  MemoryBase1;
 115   UINT32  MemoryLimit1;
 116   UINT32  IoBase0;
 117   UINT32  IoLimit0;             // I/O Base Register 0
 118   UINT32  IoBase1;              // I/O Limit Register 0
 119   UINT32  IoLimit1;
 120   UINT8   InterruptLine;        // Interrupt Line
 121   UINT8   InterruptPin;         // Interrupt Pin
 122   UINT16  BridgeControl;        // Bridge Control
 123 } PCI_CARDBUS_CONTROL_REGISTER;
 124
 125 //
 126 // Definitions of PCI class bytes and manipulation macros.
 127 //
 128 #define PCI_CLASS_OLD                 0x00
 129 #define PCI_CLASS_OLD_OTHER           0x00
 130 #define PCI_CLASS_OLD_VGA             0x01
 131
 132 #define PCI_CLASS_MASS_STORAGE        0x01
 133 #define PCI_CLASS_MASS_STORAGE_SCSI   0x00
 134 #define PCI_CLASS_MASS_STORAGE_IDE    0x01  // obsolete
 135 #define PCI_CLASS_IDE                 0x01
 136 #define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
 137 #define PCI_CLASS_MASS_STORAGE_IPI    0x03
 138 #define PCI_CLASS_MASS_STORAGE_RAID   0x04
 139 #define PCI_CLASS_MASS_STORAGE_OTHER  0x80
 140
 141 #define PCI_CLASS_NETWORK             0x02
 142 #define PCI_CLASS_NETWORK_ETHERNET    0x00
 143 #define PCI_CLASS_ETHERNET            0x00  // obsolete
 144 #define PCI_CLASS_NETWORK_TOKENRING   0x01
 145 #define PCI_CLASS_NETWORK_FDDI        0x02
 146 #define PCI_CLASS_NETWORK_ATM         0x03
 147 #define PCI_CLASS_NETWORK_ISDN        0x04
 148 #define PCI_CLASS_NETWORK_OTHER       0x80
 149
 150 #define PCI_CLASS_DISPLAY             0x03
 151 #define PCI_CLASS_DISPLAY_CTRL        0x03  // obsolete
 152 #define PCI_CLASS_DISPLAY_VGA         0x00
 153 #define PCI_CLASS_VGA                 0x00  // obsolete
 154 #define PCI_CLASS_DISPLAY_XGA         0x01
 155 #define PCI_CLASS_DISPLAY_3D          0x02
 156 #define PCI_CLASS_DISPLAY_OTHER       0x80
 157 #define PCI_CLASS_DISPLAY_GFX         0x80
 158 #define PCI_CLASS_GFX                 0x80  // obsolete
 159 #define PCI_CLASS_BRIDGE              0x06
 160 #define PCI_CLASS_BRIDGE_HOST         0x00
 161 #define PCI_CLASS_BRIDGE_ISA          0x01
 162 #define PCI_CLASS_ISA                 0x01  // obsolete
 163 #define PCI_CLASS_BRIDGE_EISA         0x02
 164 #define PCI_CLASS_BRIDGE_MCA          0x03
 165 #define PCI_CLASS_BRIDGE_P2P          0x04
 166 #define PCI_CLASS_BRIDGE_PCMCIA       0x05
 167 #define PCI_CLASS_BRIDGE_NUBUS        0x06
 168 #define PCI_CLASS_BRIDGE_CARDBUS      0x07
 169 #define PCI_CLASS_BRIDGE_RACEWAY      0x08
 170 #define PCI_CLASS_BRIDGE_ISA_PDECODE  0x80
 171 #define PCI_CLASS_ISA_POSITIVE_DECODE 0x80  // obsolete
 172
 173 #define PCI_CLASS_SCC                 0x07  // Simple communications controllers
 174 #define PCI_SUBCLASS_SERIAL           0x00
 175 #define PCI_IF_GENERIC_XT             0x00
 176 #define PCI_IF_16450                  0x01
 177 #define PCI_IF_16550                  0x02
 178 #define PCI_IF_16650                  0x03
 179 #define PCI_IF_16750                  0x04
 180 #define PCI_IF_16850                  0x05
 181 #define PCI_IF_16950                  0x06
 182 #define PCI_SUBCLASS_PARALLEL         0x01
 183 #define PCI_IF_PARALLEL_PORT          0x00
 184 #define PCI_IF_BI_DIR_PARALLEL_PORT   0x01
 185 #define PCI_IF_ECP_PARALLEL_PORT      0x02
 186 #define PCI_IF_1284_CONTROLLER        0x03
 187 #define PCI_IF_1284_DEVICE            0xFE
 188 #define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
 189 #define PCI_SUBCLASS_MODEM            0x03
 190 #define PCI_IF_GENERIC_MODEM          0x00
 191 #define PCI_IF_16450_MODEM            0x01
 192 #define PCI_IF_16550_MODEM            0x02
 193 #define PCI_IF_16650_MODEM            0x03
 194 #define PCI_IF_16750_MODEM            0x04
 195 #define PCI_SUBCLASS_OTHER            0x80
 196
 197 #define PCI_CLASS_SYSTEM_PERIPHERAL   0x08
 198 #define PCI_SUBCLASS_PIC              0x00
 199 #define PCI_IF_8259_PIC               0x00
 200 #define PCI_IF_ISA_PIC                0x01
 201 #define PCI_IF_EISA_PIC               0x02
 202 #define PCI_IF_APIC_CONTROLLER        0x10 // I/O APIC interrupt controller , 32 bye none-prefectable memory.
 203 #define PCI_IF_APIC_CONTROLLER2       0x20
 204 #define PCI_SUBCLASS_TIMER            0x02
 205 #define PCI_IF_8254_TIMER             0x00
 206 #define PCI_IF_ISA_TIMER              0x01
 207 #define PCI_EISA_TIMER                0x02
 208 #define PCI_SUBCLASS_RTC              0x03
 209 #define PCI_IF_GENERIC_RTC            0x00
 210 #define PCI_IF_ISA_RTC                0x00
 211 #define PCI_SUBCLASS_PNP_CONTROLLER   0x04 // HotPlug Controller
 212
 213 #define PCI_CLASS_INPUT_DEVICE        0x09
 214 #define PCI_SUBCLASS_KEYBOARD         0x00
 215 #define PCI_SUBCLASS_PEN              0x01
 216 #define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
 217 #define PCI_SUBCLASS_SCAN_CONTROLLER  0x03
 218 #define PCI_SUBCLASS_GAMEPORT         0x04
 219
 220 #define PCI_CLASS_DOCKING_STATION     0x0A
 221
 222 #define PCI_CLASS_PROCESSOR           0x0B
 223 #define PCI_SUBCLASS_PROC_386         0x00
 224 #define PCI_SUBCLASS_PROC_486         0x01
 225 #define PCI_SUBCLASS_PROC_PENTIUM     0x02
 226 #define PCI_SUBCLASS_PROC_ALPHA       0x10
 227 #define PCI_SUBCLASS_PROC_POWERPC     0x20
 228 #define PCI_SUBCLASS_PROC_MIPS        0x30
 229 #define PCI_SUBCLASS_PROC_CO_PORC     0x40 // Co-Processor
 230
 231 #define PCI_CLASS_SERIAL              0x0C
 232 #define PCI_CLASS_SERIAL_FIREWIRE     0x00
 233 #define PCI_CLASS_SERIAL_ACCESS_BUS   0x01
 234 #define PCI_CLASS_SERIAL_SSA          0x02
 235 #define PCI_CLASS_SERIAL_USB          0x03
 236 #define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
 237 #define PCI_CLASS_SERIAL_SMB          0x05
 238
 239 #define PCI_CLASS_WIRELESS            0x0D
 240 #define PCI_SUBCLASS_IRDA             0x00
 241 #define PCI_SUBCLASS_IR               0x01
 242 #define PCI_SUBCLASS_RF               0x02
 243
 244 #define PCI_CLASS_INTELLIGENT_IO      0x0E
 245
 246 #define PCI_CLASS_SATELLITE           0x0F
 247 #define PCI_SUBCLASS_TV               0x01
 248 #define PCI_SUBCLASS_AUDIO            0x02
 249 #define PCI_SUBCLASS_VOICE            0x03
 250 #define PCI_SUBCLASS_DATA             0x04
 251
 252 #define PCI_SECURITY_CONTROLLER       0x10 // Encryption and decryption controller
 253 #define PCI_SUBCLASS_NET_COMPUT       0x00
 254 #define PCI_SUBCLASS_ENTERTAINMENT    0x10
 255
 256 #define PCI_CLASS_DPIO                0x11
 257
 258 #define IS_CLASS1(_p, c)              ((_p)->Hdr.ClassCode[2] == (c))
 259 #define IS_CLASS2(_p, c, s)           (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
 260 #define IS_CLASS3(_p, c, s, p)        (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
 261
 262 #define IS_PCI_DISPLAY(_p)            IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
 263 #define IS_PCI_VGA(_p)                IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 0)
 264 #define IS_PCI_8514(_p)               IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 1)
 265 #define IS_PCI_GFX(_p)                IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_GFX, 0)
 266 #define IS_PCI_OLD(_p)                IS_CLASS1 (_p, PCI_CLASS_OLD)
 267 #define IS_PCI_OLD_VGA(_p)            IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
 268 #define IS_PCI_IDE(_p)                IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
 269 #define IS_PCI_SCSI(_p)               IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI, 0)
 270 #define IS_PCI_RAID(_p)               IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID, 0)
 271 #define IS_PCI_LPC(_p)                IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA, 0)
 272 #define IS_PCI_P2P(_p)                IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 0)
 273 #define IS_PCI_P2P_SUB(_p)            IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 1)
 274 #define IS_PCI_USB(_p)                IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
 275
 276 #define HEADER_TYPE_DEVICE            0x00
 277 #define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
 278 #define HEADER_TYPE_CARDBUS_BRIDGE    0x02
 279
 280 #define HEADER_TYPE_MULTI_FUNCTION    0x80
 281 #define HEADER_LAYOUT_CODE            0x7f
 282
 283 #define IS_PCI_BRIDGE(_p)             (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
 284 #define IS_CARDBUS_BRIDGE(_p)         (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
 285 #define IS_PCI_MULTI_FUNC(_p)         ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
 286
 287 #define PCI_DEVICE_ROMBAR             0x30
 288 #define PCI_BRIDGE_ROMBAR             0x38
 289
 290 #define PCI_MAX_BAR                   0x0006
 291 #define PCI_MAX_CONFIG_OFFSET         0x0100
 292
 293 #define PCI_VENDOR_ID_OFFSET                        0x00
 294 #define PCI_DEVICE_ID_OFFSET                        0x02
 295 #define PCI_COMMAND_OFFSET                          0x04
 296 #define PCI_PRIMARY_STATUS_OFFSET                   0x06
 297 #define PCI_REVISION_ID_OFFSET                      0x08
 298 #define PCI_CLASSCODE_OFFSET                        0x09
 299 #define PCI_CACHELINE_SIZE_OFFSET                   0x0C
 300 #define PCI_LATENCY_TIMER_OFFSET                    0x0D
 301 #define PCI_HEADER_TYPE_OFFSET                      0x0E
 302 #define PCI_BIST_OFFSET                             0x0F
 303 #define PCI_BASE_ADDRESSREG_OFFSET                  0x10
 304 #define PCI_CARDBUS_CIS_OFFSET                      0x28
 305 #define PCI_SVID_OFFSET                             0x2C // SubSystem Vendor id
 306 #define PCI_SUBSYSTEM_VENDOR_ID_OFFSET              0x2C
 307 #define PCI_SID_OFFSET                              0x2E // SubSystem ID
 308 #define PCI_SUBSYSTEM_ID_OFFSET                     0x2E
 309 #define PCI_EXPANSION_ROM_BASE                      0x30
 310 #define PCI_CAPBILITY_POINTER_OFFSET                0x34
 311 #define PCI_INT_LINE_OFFSET                         0x3C // Interrupt Line Register
 312 #define PCI_INT_PIN_OFFSET                          0x3D // Interrupt Pin Register
 313 #define PCI_MAXGNT_OFFSET                           0x3E // Max Grant Register
 314 #define PCI_MAXLAT_OFFSET                           0x3F // Max Latency Register
 315
 316 #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET          0x3E
 317 #define PCI_BRIDGE_STATUS_REGISTER_OFFSET           0x1E
 318
 319 #define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET      0x18
 320 #define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET    0x19
 321 #define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET  0x1a
 322
 323 typedef union {
 324   struct {
 325     UINT32  Reg : 8;
 326     UINT32  Func : 3;
 327     UINT32  Dev : 5;
 328     UINT32  Bus : 8;
 329     UINT32  Reserved : 7;
 330     UINT32  Enable : 1;
 331   } Bits;
 332   UINT32  Uint32;
 333 } PCI_CONFIG_ACCESS_CF8;
 334
 335 #pragma pack()
 336
 337 #define PCI_EXPANSION_ROM_HEADER_SIGNATURE              0xaa55
 338 #define PCI_DATA_STRUCTURE_SIGNATURE                    SIGNATURE_32 ('P', 'C', 'I', 'R')
 339 #define PCI_CODE_TYPE_PCAT_IMAGE                        0x00
 340 #define PCI_CODE_TYPE_EFI_IMAGE                         0x03
 341 #define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED         0x0001
 342
 343 #define EFI_PCI_COMMAND_IO_SPACE                        0x0001
 344 #define EFI_PCI_COMMAND_MEMORY_SPACE                    0x0002
 345 #define EFI_PCI_COMMAND_BUS_MASTER                      0x0004
 346 #define EFI_PCI_COMMAND_SPECIAL_CYCLE                   0x0008
 347 #define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE     0x0010
 348 #define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP               0x0020
 349 #define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND            0x0040
 350 #define EFI_PCI_COMMAND_STEPPING_CONTROL                0x0080
 351 #define EFI_PCI_COMMAND_SERR                            0x0100
 352 #define EFI_PCI_COMMAND_FAST_BACK_TO_BACK               0x0200
 353
 354 #define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE    0x0001
 355 #define EFI_PCI_BRIDGE_CONTROL_SERR                     0x0002
 356 #define EFI_PCI_BRIDGE_CONTROL_ISA                      0x0004
 357 #define EFI_PCI_BRIDGE_CONTROL_VGA                      0x0008
 358 #define EFI_PCI_BRIDGE_CONTROL_VGA_16                   0x0010
 359 #define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT             0x0020
 360 #define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS      0x0040
 361 #define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK        0x0080
 362 #define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER    0x0100
 363 #define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER  0x0200
 364 #define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS             0x0400
 365 #define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR       0x0800
 366
 367 //
 368 // Following are the PCI-CARDBUS bridge control bit
 369 //
 370 #define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE       0x0080
 371 #define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE   0x0100
 372 #define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE   0x0200
 373 #define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE 0x0400
 374
 375 //
 376 // Following are the PCI status control bit
 377 //
 378 #define EFI_PCI_STATUS_CAPABILITY             0x0010
 379 #define EFI_PCI_STATUS_66MZ_CAPABLE           0x0020
 380 #define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE     0x0080
 381 #define EFI_PCI_MASTER_DATA_PARITY_ERROR      0x0100
 382
 383 #define EFI_PCI_CAPABILITY_PTR                0x34
 384 #define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
 385
 386 #pragma pack(1)
 387 typedef struct {
 388   UINT16  Signature;    // 0xaa55
 389   UINT8   Reserved[0x16];
 390   UINT16  PcirOffset;
 391 } PCI_EXPANSION_ROM_HEADER;
 392
 393 typedef struct {
 394   UINT16  Signature;    // 0xaa55
 395   UINT8   Size512;
 396   UINT8   InitEntryPoint[3];
 397   UINT8   Reserved[0x12];
 398   UINT16  PcirOffset;
 399 } EFI_LEGACY_EXPANSION_ROM_HEADER;
 400
 401 typedef struct {
 402   UINT32  Signature;    // "PCIR"
 403   UINT16  VendorId;
 404   UINT16  DeviceId;
 405   UINT16  Reserved0;
 406   UINT16  Length;
 407   UINT8   Revision;
 408   UINT8   ClassCode[3];
 409   UINT16  ImageLength;
 410   UINT16  CodeRevision;
 411   UINT8   CodeType;
 412   UINT8   Indicator;
 413   UINT16  Reserved1;
 414 } PCI_DATA_STRUCTURE;
 415
 416 //
 417 // PCI Capability List IDs and records
 418 //
 419 #define EFI_PCI_CAPABILITY_ID_PMI     0x01
 420 #define EFI_PCI_CAPABILITY_ID_AGP     0x02
 421 #define EFI_PCI_CAPABILITY_ID_VPD     0x03
 422 #define EFI_PCI_CAPABILITY_ID_SLOTID  0x04
 423 #define EFI_PCI_CAPABILITY_ID_MSI     0x05
 424 #define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
 425 #define EFI_PCI_CAPABILITY_ID_PCIX    0x07
 426
 427 typedef struct {
 428   UINT8 CapabilityID;
 429   UINT8 NextItemPtr;
 430 } EFI_PCI_CAPABILITY_HDR;
 431
 432 //
 433 // Capability EFI_PCI_CAPABILITY_ID_PMI
 434 //
 435 typedef struct {
 436   EFI_PCI_CAPABILITY_HDR  Hdr;
 437   UINT16                  PMC;
 438   UINT16                  PMCSR;
 439   UINT8                   BridgeExtention;
 440   UINT8                   Data;
 441 } EFI_PCI_CAPABILITY_PMI;
 442
 443 //
 444 // Capability EFI_PCI_CAPABILITY_ID_AGP
 445 //
 446 typedef struct {
 447   EFI_PCI_CAPABILITY_HDR  Hdr;
 448   UINT8                   Rev;
 449   UINT8                   Reserved;
 450   UINT32                  Status;
 451   UINT32                  Command;
 452 } EFI_PCI_CAPABILITY_AGP;
 453
 454 //
 455 // Capability EFI_PCI_CAPABILITY_ID_VPD
 456 //
 457 typedef struct {
 458   EFI_PCI_CAPABILITY_HDR  Hdr;
 459   UINT16                  AddrReg;
 460   UINT32                  DataReg;
 461 } EFI_PCI_CAPABILITY_VPD;
 462
 463 //
 464 // Capability EFI_PCI_CAPABILITY_ID_SLOTID
 465 //
 466 typedef struct {
 467   EFI_PCI_CAPABILITY_HDR  Hdr;
 468   UINT8                   ExpnsSlotReg;
 469   UINT8                   ChassisNo;
 470 } EFI_PCI_CAPABILITY_SLOTID;
 471
 472 //
 473 // Capability EFI_PCI_CAPABILITY_ID_MSI
 474 //
 475 typedef struct {
 476   EFI_PCI_CAPABILITY_HDR  Hdr;
 477   UINT16                  MsgCtrlReg;
 478   UINT32                  MsgAddrReg;
 479   UINT16                  MsgDataReg;
 480 } EFI_PCI_CAPABILITY_MSI32;
 481
 482 typedef struct {
 483   EFI_PCI_CAPABILITY_HDR  Hdr;
 484   UINT16                  MsgCtrlReg;
 485   UINT32                  MsgAddrRegLsdw;
 486   UINT32                  MsgAddrRegMsdw;
 487   UINT16                  MsgDataReg;
 488 } EFI_PCI_CAPABILITY_MSI64;
 489
 490 //
 491 // Capability EFI_PCI_CAPABILITY_ID_HOTPLUG
 492 //
 493 typedef struct {
 494   EFI_PCI_CAPABILITY_HDR  Hdr;
 495   //
 496   // not finished - fields need to go here
 497   //
 498 } EFI_PCI_CAPABILITY_HOTPLUG;
 499
 500 //
 501 // Capability EFI_PCI_CAPABILITY_ID_PCIX
 502 //
 503 typedef struct {
 504   EFI_PCI_CAPABILITY_HDR  Hdr;
 505   UINT16                  CommandReg;
 506   UINT32                  StatusReg;
 507 } EFI_PCI_CAPABILITY_PCIX;
 508
 509 typedef struct {
 510   EFI_PCI_CAPABILITY_HDR  Hdr;
 511   UINT16                  SecStatusReg;
 512   UINT32                  StatusReg;
 513   UINT32                  SplitTransCtrlRegUp;
 514   UINT32                  SplitTransCtrlRegDn;
 515 } EFI_PCI_CAPABILITY_PCIX_BRDG;
 516
 517 #define DEVICE_ID_NOCARE    0xFFFF
 518
 519 #define PCI_ACPI_UNUSED     0
 520 #define PCI_BAR_NOCHANGE    0
 521 #define PCI_BAR_OLD_ALIGN   0xFFFFFFFFFFFFFFFFULL
 522 #define PCI_BAR_EVEN_ALIGN  0xFFFFFFFFFFFFFFFEULL
 523 #define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL
 524 #define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL
 525
 526 #define PCI_BAR_IDX0        0x00
 527 #define PCI_BAR_IDX1        0x01
 528 #define PCI_BAR_IDX2        0x02
 529 #define PCI_BAR_IDX3        0x03
 530 #define PCI_BAR_IDX4        0x04
 531 #define PCI_BAR_IDX5        0x05
 532 #define PCI_BAR_ALL         0xFF
 533
 534 #pragma pack(pop)
 535
 536 //
 537 // NOTE: The following header files are included here for
 538 // compatibility consideration.
 539 //
 540 #include "pci23.h"
 541 #include "pci30.h"
 542 #include "EfiPci.h"
 543
 544 #endif