BeagleBoardPkg/Include/Omap3530/Omap3530PadConfiguration.h

   1 /** @file
   2
   3   Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
   4
   5   All rights reserved. This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef __OMAP3530_PAD_CONFIGURATION_H__
  16 #define __OMAP3530_PAD_CONFIGURATION_H__
  17
  18 #define SYSTEM_CONTROL_MODULE_BASE  0x48002000
  19
  20 //Pin definition
  21 #define SDRC_D0             (SYSTEM_CONTROL_MODULE_BASE + 0x030)
  22 #define SDRC_D1             (SYSTEM_CONTROL_MODULE_BASE + 0x032)
  23 #define SDRC_D2             (SYSTEM_CONTROL_MODULE_BASE + 0x034)
  24 #define SDRC_D3             (SYSTEM_CONTROL_MODULE_BASE + 0x036)
  25 #define SDRC_D4             (SYSTEM_CONTROL_MODULE_BASE + 0x038)
  26 #define SDRC_D5             (SYSTEM_CONTROL_MODULE_BASE + 0x03A)
  27 #define SDRC_D6             (SYSTEM_CONTROL_MODULE_BASE + 0x03C)
  28 #define SDRC_D7             (SYSTEM_CONTROL_MODULE_BASE + 0x03E)
  29 #define SDRC_D8             (SYSTEM_CONTROL_MODULE_BASE + 0x040)
  30 #define SDRC_D9             (SYSTEM_CONTROL_MODULE_BASE + 0x042)
  31 #define SDRC_D10            (SYSTEM_CONTROL_MODULE_BASE + 0x044)
  32 #define SDRC_D11            (SYSTEM_CONTROL_MODULE_BASE + 0x046)
  33 #define SDRC_D12            (SYSTEM_CONTROL_MODULE_BASE + 0x048)
  34 #define SDRC_D13            (SYSTEM_CONTROL_MODULE_BASE + 0x04A)
  35 #define SDRC_D14            (SYSTEM_CONTROL_MODULE_BASE + 0x04C)
  36 #define SDRC_D15            (SYSTEM_CONTROL_MODULE_BASE + 0x04E)
  37 #define SDRC_D16            (SYSTEM_CONTROL_MODULE_BASE + 0x050)
  38 #define SDRC_D17            (SYSTEM_CONTROL_MODULE_BASE + 0x052)
  39 #define SDRC_D18            (SYSTEM_CONTROL_MODULE_BASE + 0x054)
  40 #define SDRC_D19            (SYSTEM_CONTROL_MODULE_BASE + 0x056)
  41 #define SDRC_D20            (SYSTEM_CONTROL_MODULE_BASE + 0x058)
  42 #define SDRC_D21            (SYSTEM_CONTROL_MODULE_BASE + 0x05A)
  43 #define SDRC_D22            (SYSTEM_CONTROL_MODULE_BASE + 0x05C)
  44 #define SDRC_D23            (SYSTEM_CONTROL_MODULE_BASE + 0x05E)
  45 #define SDRC_D24            (SYSTEM_CONTROL_MODULE_BASE + 0x060)
  46 #define SDRC_D25            (SYSTEM_CONTROL_MODULE_BASE + 0x062)
  47 #define SDRC_D26            (SYSTEM_CONTROL_MODULE_BASE + 0x064)
  48 #define SDRC_D27            (SYSTEM_CONTROL_MODULE_BASE + 0x066)
  49 #define SDRC_D28            (SYSTEM_CONTROL_MODULE_BASE + 0x068)
  50 #define SDRC_D29            (SYSTEM_CONTROL_MODULE_BASE + 0x06A)
  51 #define SDRC_D30            (SYSTEM_CONTROL_MODULE_BASE + 0x06C)
  52 #define SDRC_D31            (SYSTEM_CONTROL_MODULE_BASE + 0x06E)
  53 #define SDRC_CLK            (SYSTEM_CONTROL_MODULE_BASE + 0x070)
  54 #define SDRC_DQS0           (SYSTEM_CONTROL_MODULE_BASE + 0x072)
  55 #define SDRC_CKE0           (SYSTEM_CONTROL_MODULE_BASE + 0x262)
  56 #define SDRC_CKE1           (SYSTEM_CONTROL_MODULE_BASE + 0x264)
  57 #define SDRC_DQS1           (SYSTEM_CONTROL_MODULE_BASE + 0x074)
  58 #define SDRC_DQS2           (SYSTEM_CONTROL_MODULE_BASE + 0x076)
  59 #define SDRC_DQS3           (SYSTEM_CONTROL_MODULE_BASE + 0x078)
  60 #define GPMC_A1             (SYSTEM_CONTROL_MODULE_BASE + 0x07A)
  61 #define GPMC_A2             (SYSTEM_CONTROL_MODULE_BASE + 0x07C)
  62 #define GPMC_A3             (SYSTEM_CONTROL_MODULE_BASE + 0x07E)
  63 #define GPMC_A4             (SYSTEM_CONTROL_MODULE_BASE + 0x080)
  64 #define GPMC_A5             (SYSTEM_CONTROL_MODULE_BASE + 0x082)
  65 #define GPMC_A6             (SYSTEM_CONTROL_MODULE_BASE + 0x084)
  66 #define GPMC_A7             (SYSTEM_CONTROL_MODULE_BASE + 0x086)
  67 #define GPMC_A8             (SYSTEM_CONTROL_MODULE_BASE + 0x088)
  68 #define GPMC_A9             (SYSTEM_CONTROL_MODULE_BASE + 0x08A)
  69 #define GPMC_A10            (SYSTEM_CONTROL_MODULE_BASE + 0x08C)
  70 #define GPMC_D0             (SYSTEM_CONTROL_MODULE_BASE + 0x08E)
  71 #define GPMC_D1             (SYSTEM_CONTROL_MODULE_BASE + 0x090)
  72 #define GPMC_D2             (SYSTEM_CONTROL_MODULE_BASE + 0x092)
  73 #define GPMC_D3             (SYSTEM_CONTROL_MODULE_BASE + 0x094)
  74 #define GPMC_D4             (SYSTEM_CONTROL_MODULE_BASE + 0x096)
  75 #define GPMC_D5             (SYSTEM_CONTROL_MODULE_BASE + 0x098)
  76 #define GPMC_D6             (SYSTEM_CONTROL_MODULE_BASE + 0x09A)
  77 #define GPMC_D7             (SYSTEM_CONTROL_MODULE_BASE + 0x09C)
  78 #define GPMC_D8             (SYSTEM_CONTROL_MODULE_BASE + 0x09E)
  79 #define GPMC_D9             (SYSTEM_CONTROL_MODULE_BASE + 0x0A0)
  80 #define GPMC_D10            (SYSTEM_CONTROL_MODULE_BASE + 0x0A2)
  81 #define GPMC_D11            (SYSTEM_CONTROL_MODULE_BASE + 0x0A4)
  82 #define GPMC_D12            (SYSTEM_CONTROL_MODULE_BASE + 0x0A6)
  83 #define GPMC_D13            (SYSTEM_CONTROL_MODULE_BASE + 0x0A8)
  84 #define GPMC_D14            (SYSTEM_CONTROL_MODULE_BASE + 0x0AA)
  85 #define GPMC_D15            (SYSTEM_CONTROL_MODULE_BASE + 0x0AC)
  86 #define GPMC_NCS0           (SYSTEM_CONTROL_MODULE_BASE + 0x0AE)
  87 #define GPMC_NCS1           (SYSTEM_CONTROL_MODULE_BASE + 0x0B0)
  88 #define GPMC_NCS2           (SYSTEM_CONTROL_MODULE_BASE + 0x0B2)
  89 #define GPMC_NCS3           (SYSTEM_CONTROL_MODULE_BASE + 0x0B4)
  90 #define GPMC_NCS4           (SYSTEM_CONTROL_MODULE_BASE + 0x0B6)
  91 #define GPMC_NCS5           (SYSTEM_CONTROL_MODULE_BASE + 0x0B8)
  92 #define GPMC_NCS6           (SYSTEM_CONTROL_MODULE_BASE + 0x0BA)
  93 #define GPMC_NCS7           (SYSTEM_CONTROL_MODULE_BASE + 0x0BC)
  94 #define GPMC_CLK            (SYSTEM_CONTROL_MODULE_BASE + 0x0BE)
  95 #define GPMC_NADV_ALE       (SYSTEM_CONTROL_MODULE_BASE + 0x0C0)
  96 #define GPMC_NOE            (SYSTEM_CONTROL_MODULE_BASE + 0x0C2)
  97 #define GPMC_NWE            (SYSTEM_CONTROL_MODULE_BASE + 0x0C4)
  98 #define GPMC_NBE0_CLE       (SYSTEM_CONTROL_MODULE_BASE + 0x0C6)
  99 #define GPMC_NBE1           (SYSTEM_CONTROL_MODULE_BASE + 0x0C8)
 100 #define GPMC_NWP            (SYSTEM_CONTROL_MODULE_BASE + 0x0CA)
 101 #define GPMC_WAIT0          (SYSTEM_CONTROL_MODULE_BASE + 0x0CC)
 102 #define GPMC_WAIT1          (SYSTEM_CONTROL_MODULE_BASE + 0x0CE)
 103 #define GPMC_WAIT2          (SYSTEM_CONTROL_MODULE_BASE + 0x0D0)
 104 #define GPMC_WAIT3          (SYSTEM_CONTROL_MODULE_BASE + 0x0D2)
 105 #define DSS_PCLK            (SYSTEM_CONTROL_MODULE_BASE + 0x0D4)
 106 #define DSS_HSYNC           (SYSTEM_CONTROL_MODULE_BASE + 0x0D6)
 107 #define DSS_PSYNC           (SYSTEM_CONTROL_MODULE_BASE + 0x0D8)
 108 #define DSS_ACBIAS          (SYSTEM_CONTROL_MODULE_BASE + 0x0DA)
 109 #define DSS_DATA0           (SYSTEM_CONTROL_MODULE_BASE + 0x0DC)
 110 #define DSS_DATA1           (SYSTEM_CONTROL_MODULE_BASE + 0x0DE)
 111 #define DSS_DATA2           (SYSTEM_CONTROL_MODULE_BASE + 0x0E0)
 112 #define DSS_DATA3           (SYSTEM_CONTROL_MODULE_BASE + 0x0E2)
 113 #define DSS_DATA4           (SYSTEM_CONTROL_MODULE_BASE + 0x0E4)
 114 #define DSS_DATA5           (SYSTEM_CONTROL_MODULE_BASE + 0x0E6)
 115 #define DSS_DATA6           (SYSTEM_CONTROL_MODULE_BASE + 0x0E8)
 116 #define DSS_DATA7           (SYSTEM_CONTROL_MODULE_BASE + 0x0EA)
 117 #define DSS_DATA8           (SYSTEM_CONTROL_MODULE_BASE + 0x0EC)
 118 #define DSS_DATA9           (SYSTEM_CONTROL_MODULE_BASE + 0x0EE)
 119 #define DSS_DATA10          (SYSTEM_CONTROL_MODULE_BASE + 0x0F0)
 120 #define DSS_DATA11          (SYSTEM_CONTROL_MODULE_BASE + 0x0F2)
 121 #define DSS_DATA12          (SYSTEM_CONTROL_MODULE_BASE + 0x0F4)
 122 #define DSS_DATA13          (SYSTEM_CONTROL_MODULE_BASE + 0x0F6)
 123 #define DSS_DATA14          (SYSTEM_CONTROL_MODULE_BASE + 0x0F8)
 124 #define DSS_DATA15          (SYSTEM_CONTROL_MODULE_BASE + 0x0FA)
 125 #define DSS_DATA16          (SYSTEM_CONTROL_MODULE_BASE + 0x0FC)
 126 #define DSS_DATA17          (SYSTEM_CONTROL_MODULE_BASE + 0x0FE)
 127 #define DSS_DATA18          (SYSTEM_CONTROL_MODULE_BASE + 0x100)
 128 #define DSS_DATA19          (SYSTEM_CONTROL_MODULE_BASE + 0x102)
 129 #define DSS_DATA20          (SYSTEM_CONTROL_MODULE_BASE + 0x104)
 130 #define DSS_DATA21          (SYSTEM_CONTROL_MODULE_BASE + 0x106)
 131 #define DSS_DATA22          (SYSTEM_CONTROL_MODULE_BASE + 0x108)
 132 #define DSS_DATA23          (SYSTEM_CONTROL_MODULE_BASE + 0x10A)
 133 #define CAM_HS              (SYSTEM_CONTROL_MODULE_BASE + 0x10C)
 134 #define CAM_VS              (SYSTEM_CONTROL_MODULE_BASE + 0x10E)
 135 #define CAM_XCLKA           (SYSTEM_CONTROL_MODULE_BASE + 0x110)
 136 #define CAM_PCLK            (SYSTEM_CONTROL_MODULE_BASE + 0x112)
 137 #define CAM_FLD             (SYSTEM_CONTROL_MODULE_BASE + 0x114)
 138 #define CAM_D0              (SYSTEM_CONTROL_MODULE_BASE + 0x116)
 139 #define CAM_D1              (SYSTEM_CONTROL_MODULE_BASE + 0x118)
 140 #define CAM_D2              (SYSTEM_CONTROL_MODULE_BASE + 0x11A)
 141 #define CAM_D3              (SYSTEM_CONTROL_MODULE_BASE + 0x11C)
 142 #define CAM_D4              (SYSTEM_CONTROL_MODULE_BASE + 0x11E)
 143 #define CAM_D5              (SYSTEM_CONTROL_MODULE_BASE + 0x120)
 144 #define CAM_D6              (SYSTEM_CONTROL_MODULE_BASE + 0x122)
 145 #define CAM_D7              (SYSTEM_CONTROL_MODULE_BASE + 0x124)
 146 #define CAM_D8              (SYSTEM_CONTROL_MODULE_BASE + 0x126)
 147 #define CAM_D9              (SYSTEM_CONTROL_MODULE_BASE + 0x128)
 148 #define CAM_D10             (SYSTEM_CONTROL_MODULE_BASE + 0x12A)
 149 #define CAM_D11             (SYSTEM_CONTROL_MODULE_BASE + 0x12C)
 150 #define CAM_XCLKB           (SYSTEM_CONTROL_MODULE_BASE + 0x12E)
 151 #define CAM_WEN             (SYSTEM_CONTROL_MODULE_BASE + 0x130)
 152 #define CAM_STROBE          (SYSTEM_CONTROL_MODULE_BASE + 0x132)
 153 #define CSI2_DX0            (SYSTEM_CONTROL_MODULE_BASE + 0x134)
 154 #define CSI2_DY0            (SYSTEM_CONTROL_MODULE_BASE + 0x136)
 155 #define CSI2_DX1            (SYSTEM_CONTROL_MODULE_BASE + 0x138)
 156 #define CSI2_DY1            (SYSTEM_CONTROL_MODULE_BASE + 0x13A)
 157 #define MCBSP2_FSX          (SYSTEM_CONTROL_MODULE_BASE + 0x13C)
 158 #define MCBSP2_CLKX         (SYSTEM_CONTROL_MODULE_BASE + 0x13E)
 159 #define MCBSP2_DR           (SYSTEM_CONTROL_MODULE_BASE + 0x140)
 160 #define MCBSP2_DX           (SYSTEM_CONTROL_MODULE_BASE + 0x142)
 161 #define MMC1_CLK            (SYSTEM_CONTROL_MODULE_BASE + 0x144)
 162 #define MMC1_CMD            (SYSTEM_CONTROL_MODULE_BASE + 0x146)
 163 #define MMC1_DAT0           (SYSTEM_CONTROL_MODULE_BASE + 0x148)
 164 #define MMC1_DAT1           (SYSTEM_CONTROL_MODULE_BASE + 0x14A)
 165 #define MMC1_DAT2           (SYSTEM_CONTROL_MODULE_BASE + 0x14C)
 166 #define MMC1_DAT3           (SYSTEM_CONTROL_MODULE_BASE + 0x14E)
 167 #define MMC1_DAT4           (SYSTEM_CONTROL_MODULE_BASE + 0x150)
 168 #define MMC1_DAT5           (SYSTEM_CONTROL_MODULE_BASE + 0x152)
 169 #define MMC1_DAT6           (SYSTEM_CONTROL_MODULE_BASE + 0x154)
 170 #define MMC1_DAT7           (SYSTEM_CONTROL_MODULE_BASE + 0x156)
 171 #define MMC2_CLK            (SYSTEM_CONTROL_MODULE_BASE + 0x158)
 172 #define MMC2_CMD            (SYSTEM_CONTROL_MODULE_BASE + 0x15A)
 173 #define MMC2_DAT0           (SYSTEM_CONTROL_MODULE_BASE + 0x15C)
 174 #define MMC2_DAT1           (SYSTEM_CONTROL_MODULE_BASE + 0x15E)
 175 #define MMC2_DAT2           (SYSTEM_CONTROL_MODULE_BASE + 0x160)
 176 #define MMC2_DAT3           (SYSTEM_CONTROL_MODULE_BASE + 0x162)
 177 #define MMC2_DAT4           (SYSTEM_CONTROL_MODULE_BASE + 0x164)
 178 #define MMC2_DAT5           (SYSTEM_CONTROL_MODULE_BASE + 0x166)
 179 #define MMC2_DAT6           (SYSTEM_CONTROL_MODULE_BASE + 0x168)
 180 #define MMC2_DAT7           (SYSTEM_CONTROL_MODULE_BASE + 0x16A)
 181 #define MCBSP3_DX           (SYSTEM_CONTROL_MODULE_BASE + 0x16C)
 182 #define MCBSP3_DR           (SYSTEM_CONTROL_MODULE_BASE + 0x16E)
 183 #define MCBSP3_CLKX         (SYSTEM_CONTROL_MODULE_BASE + 0x170)
 184 #define MCBSP3_FSX          (SYSTEM_CONTROL_MODULE_BASE + 0x172)
 185 #define UART2_CTS           (SYSTEM_CONTROL_MODULE_BASE + 0x174)
 186 #define UART2_RTS           (SYSTEM_CONTROL_MODULE_BASE + 0x176)
 187 #define UART2_TX            (SYSTEM_CONTROL_MODULE_BASE + 0x178)
 188 #define UART2_RX            (SYSTEM_CONTROL_MODULE_BASE + 0x17A)
 189 #define UART1_TX            (SYSTEM_CONTROL_MODULE_BASE + 0x17C)
 190 #define UART1_RTS           (SYSTEM_CONTROL_MODULE_BASE + 0x17E)
 191 #define UART1_CTS           (SYSTEM_CONTROL_MODULE_BASE + 0x180)
 192 #define UART1_RX            (SYSTEM_CONTROL_MODULE_BASE + 0x182)
 193 #define MCBSP4_CLKX         (SYSTEM_CONTROL_MODULE_BASE + 0x184)
 194 #define MCBSP4_DR           (SYSTEM_CONTROL_MODULE_BASE + 0x186)
 195 #define MCBSP4_DX           (SYSTEM_CONTROL_MODULE_BASE + 0x188)
 196 #define MCBSP4_FSX          (SYSTEM_CONTROL_MODULE_BASE + 0x18A)
 197 #define MCBSP1_CLKR         (SYSTEM_CONTROL_MODULE_BASE + 0x18C)
 198 #define MCBSP1_FSR          (SYSTEM_CONTROL_MODULE_BASE + 0x18E)
 199 #define MCBSP1_DX           (SYSTEM_CONTROL_MODULE_BASE + 0x190)
 200 #define MCBSP1_DR           (SYSTEM_CONTROL_MODULE_BASE + 0x192)
 201 #define MCBSP1_CLKS         (SYSTEM_CONTROL_MODULE_BASE + 0x194)
 202 #define MCBSP1_FSX          (SYSTEM_CONTROL_MODULE_BASE + 0x196)
 203 #define MCBSP1_CLKX         (SYSTEM_CONTROL_MODULE_BASE + 0x198)
 204 #define UART3_CTS_RCTX      (SYSTEM_CONTROL_MODULE_BASE + 0x19A)
 205 #define UART3_RTS_SD        (SYSTEM_CONTROL_MODULE_BASE + 0x19C)
 206 #define UART3_RX_IRRX       (SYSTEM_CONTROL_MODULE_BASE + 0x19E)
 207 #define UART3_TX_IRTX       (SYSTEM_CONTROL_MODULE_BASE + 0x1A0)
 208 #define HSUSB0_CLK          (SYSTEM_CONTROL_MODULE_BASE + 0x1A2)
 209 #define HSUSB0_STP          (SYSTEM_CONTROL_MODULE_BASE + 0x1A4)
 210 #define HSUSB0_DIR          (SYSTEM_CONTROL_MODULE_BASE + 0x1A6)
 211 #define HSUSB0_NXT          (SYSTEM_CONTROL_MODULE_BASE + 0x1A8)
 212 #define HSUSB0_DATA0        (SYSTEM_CONTROL_MODULE_BASE + 0x1AA)
 213 #define HSUSB0_DATA1        (SYSTEM_CONTROL_MODULE_BASE + 0x1AC)
 214 #define HSUSB0_DATA2        (SYSTEM_CONTROL_MODULE_BASE + 0x1AE)
 215 #define HSUSB0_DATA3        (SYSTEM_CONTROL_MODULE_BASE + 0x1B0)
 216 #define HSUSB0_DATA4        (SYSTEM_CONTROL_MODULE_BASE + 0x1B2)
 217 #define HSUSB0_DATA5        (SYSTEM_CONTROL_MODULE_BASE + 0x1B4)
 218 #define HSUSB0_DATA6        (SYSTEM_CONTROL_MODULE_BASE + 0x1B6)
 219 #define HSUSB0_DATA7        (SYSTEM_CONTROL_MODULE_BASE + 0x1B8)
 220 #define I2C1_SCL            (SYSTEM_CONTROL_MODULE_BASE + 0x1BA)
 221 #define I2C1_SDA            (SYSTEM_CONTROL_MODULE_BASE + 0x1BC)
 222 #define I2C2_SCL            (SYSTEM_CONTROL_MODULE_BASE + 0x1BE)
 223 #define I2C2_SDA            (SYSTEM_CONTROL_MODULE_BASE + 0x1C0)
 224 #define I2C3_SCL            (SYSTEM_CONTROL_MODULE_BASE + 0x1C2)
 225 #define I2C3_SDA            (SYSTEM_CONTROL_MODULE_BASE + 0x1C4)
 226 #define HDQ_SIO             (SYSTEM_CONTROL_MODULE_BASE + 0x1C6)
 227 #define MCSPI1_CLK          (SYSTEM_CONTROL_MODULE_BASE + 0x1C8)
 228 #define MCSPI1_SIMO         (SYSTEM_CONTROL_MODULE_BASE + 0x1CA)
 229 #define MCSPI1_SOMI         (SYSTEM_CONTROL_MODULE_BASE + 0x1CC)
 230 #define MCSPI1_CS0          (SYSTEM_CONTROL_MODULE_BASE + 0x1CE)
 231 #define MCSPI1_CS1          (SYSTEM_CONTROL_MODULE_BASE + 0x1D0)
 232 #define MCSPI1_CS2          (SYSTEM_CONTROL_MODULE_BASE + 0x1D2)
 233 #define MCSPI1_CS3          (SYSTEM_CONTROL_MODULE_BASE + 0x1D4)
 234 #define MCSPI2_CLK          (SYSTEM_CONTROL_MODULE_BASE + 0x1D6)
 235 #define MCSPI2_SIMO         (SYSTEM_CONTROL_MODULE_BASE + 0x1D8)
 236 #define MCSPI2_SOMI         (SYSTEM_CONTROL_MODULE_BASE + 0x1DA)
 237 #define MCSPI2_CS0          (SYSTEM_CONTROL_MODULE_BASE + 0x1DC)
 238 #define MCSPI2_CS1          (SYSTEM_CONTROL_MODULE_BASE + 0x1DE)
 239 #define SYS_NIRQ            (SYSTEM_CONTROL_MODULE_BASE + 0x1E0)
 240 #define SYS_CLKOUT2         (SYSTEM_CONTROL_MODULE_BASE + 0x1E2)
 241 #define ETK_CLK             (SYSTEM_CONTROL_MODULE_BASE + 0x5D8)
 242 #define ETK_CTL             (SYSTEM_CONTROL_MODULE_BASE + 0x5DA)
 243 #define ETK_D0              (SYSTEM_CONTROL_MODULE_BASE + 0x5DC)
 244 #define ETK_D1              (SYSTEM_CONTROL_MODULE_BASE + 0x5DE)
 245 #define ETK_D2              (SYSTEM_CONTROL_MODULE_BASE + 0x5E0)
 246 #define ETK_D3              (SYSTEM_CONTROL_MODULE_BASE + 0x5E2)
 247 #define ETK_D4              (SYSTEM_CONTROL_MODULE_BASE + 0x5E4)
 248 #define ETK_D5              (SYSTEM_CONTROL_MODULE_BASE + 0x5E6)
 249 #define ETK_D6              (SYSTEM_CONTROL_MODULE_BASE + 0x5E8)
 250 #define ETK_D7              (SYSTEM_CONTROL_MODULE_BASE + 0x5EA)
 251 #define ETK_D8              (SYSTEM_CONTROL_MODULE_BASE + 0x5EC)
 252 #define ETK_D9              (SYSTEM_CONTROL_MODULE_BASE + 0x5EE)
 253 #define ETK_D10             (SYSTEM_CONTROL_MODULE_BASE + 0x5F0)
 254 #define ETK_D11             (SYSTEM_CONTROL_MODULE_BASE + 0x5F2)
 255 #define ETK_D12             (SYSTEM_CONTROL_MODULE_BASE + 0x5F4)
 256 #define ETK_D13             (SYSTEM_CONTROL_MODULE_BASE + 0x5F6)
 257 #define ETK_D14             (SYSTEM_CONTROL_MODULE_BASE + 0x5F8)
 258 #define ETK_D15             (SYSTEM_CONTROL_MODULE_BASE + 0x5FA)
 259
 260 //Mux modes
 261 #define MUXMODE0            (0x0UL)
 262 #define MUXMODE1            (0x1UL)
 263 #define MUXMODE2            (0x2UL)
 264 #define MUXMODE3            (0x3UL)
 265 #define MUXMODE4            (0x4UL)
 266 #define MUXMODE5            (0x5UL)
 267 #define MUXMODE6            (0x6UL)
 268 #define MUXMODE7            (0x7UL)
 269
 270 //Pad configuration register.
 271 #define PAD_CONFIG_MASK      (0xFFFFUL)
 272 #define MUXMODE_OFFSET       0
 273 #define MUXMODE_MASK         (0x7UL << MUXMODE_OFFSET)
 274 #define PULL_CONFIG_OFFSET   3
 275 #define PULL_CONFIG_MASK     (0x3UL << PULL_CONFIG_OFFSET)
 276 #define INPUTENABLE_OFFSET   8
 277 #define INPUTENABLE_MASK     (0x1UL << INPUTENABLE_OFFSET)
 278 #define OFFMODE_VALUE_OFFSET 9
 279 #define OFFMODE_VALUE_MASK   (0x1FUL << OFFMODE_VALUE_OFFSET)
 280 #define WAKEUP_OFFSET        14
 281 #define WAKEUP_MASK          (0x2UL << WAKEUP_OFFSET)
 282
 283 #define PULLUDDISABLE        (0x0UL << 0)
 284 #define PULLUDENABLE         (0x1UL << 0)
 285 #define PULLTYPENOSELECT     (0x0UL << 1)
 286 #define PULLTYPESELECT       (0x1UL << 1)
 287
 288 #define OUTPUT               (0x0UL) //Pin is configured in output only mode.
 289 #define INPUT                (0x1UL) //Pin is configured in bi-directional mode.
 290
 291 typedef struct {
 292   UINTN   Pin;
 293   UINTN   MuxMode;
 294   UINTN   PullConfig;
 295   UINTN   InputEnable;
 296 } PAD_CONFIGURATION;
 297
 298 #endif //__OMAP3530_PAD_CONFIGURATION_H__