BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4 #
   5 # This program and the accompanying materials
   6 # are licensed and made available under the terms and conditions of the BSD License
   7 # which accompanies this distribution.  The full text of the license may be found at
   8 # http://opensource.org/licenses/bsd-license.php
   9 #
  10 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 #
  13 #------------------------------------------------------------------------------
  14
  15 #include <AsmMacroIoLib.h>
  16 #include <Library/PcdLib.h>
  17
  18 .text
  19 .align 3
  20
  21 .globl ASM_PFX(CEntryPoint)
  22 GCC_ASM_EXPORT(_ModuleEntryPoint)
  23
  24 ASM_PFX(_ModuleEntryPoint):
  25
  26   //Disable L2 cache
  27   mrc     p15, 0, r0, c1, c0, 1   // read Auxiliary Control Register
  28   bic     r0, r0, #0x00000002     // disable L2 cache
  29   mcr     p15, 0, r0, c1, c0, 1   // store Auxiliary Control Register
  30
  31   //Enable Strict alignment checking & Instruction cache
  32   mrc     p15, 0, r0, c1, c0, 0
  33   bic     r0, r0, #0x00002300     /* clear bits 13, 9:8 (--V- --RS) */
  34   bic     r0, r0, #0x00000005     /* clear bits 0, 2 (---- -C-M) */
  35   orr     r0, r0, #0x00000002     /* set bit 1 (A) Align */
  36   orr     r0, r0, #0x00001000     /* set bit 12 (I) enable I-Cache */
  37   mcr     p15, 0, r0, c1, c0, 0
  38
  39   // Enable NEON register in case folks want to use them for optimizations (CopyMem)
  40   mrc     p15, 0, r0, c1, c0, 2
  41   orr     r0, r0, #0x00f00000   // Enable VPF access (V* instructions)
  42   mcr     p15, 0, r0, c1, c0, 2
  43   mov     r0, #0x40000000       // Set EN bit in FPEXC
  44   mcr     p10,#0x7,r0,c8,c0,#0  // msr     FPEXC,r0 in ARM assembly
  45
  46
  47   // Set CPU vectors to start of DRAM
  48   LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base
  49   mcr     p15, 0, r0, c12, c0, 0
  50   isb                               // Sync changes to control registers
  51
  52   // Fill vector table with branchs to current pc (jmp $)
  53   ldr     r1, ShouldNeverGetHere
  54   movs    r2, #0
  55 FillVectors:
  56   str     r1, [r0, r2]
  57   adds    r2, r2, #4
  58   cmp     r2, #32
  59   bne     FillVectors
  60
  61   /* before we call C code, lets setup the stack pointer in internal RAM */
  62 stack_pointer_setup:
  63
  64   //
  65   // Set stack based on PCD values. Need to do it this way to make C code work
  66   // when it runs from FLASH.
  67   //
  68   LoadConstantToReg (FixedPcdGet32(PcdPrePiStackBase) ,r2)    /* stack base arg2  */
  69   LoadConstantToReg (FixedPcdGet32(PcdPrePiStackSize) ,r3)    /* stack size arg3  */
  70   add     r4, r2, r3
  71
  72   //Enter SVC mode and set up SVC stack pointer
  73   mov     r0,#0x13|0x80|0x40
  74   msr     CPSR_c,r0
  75   mov     r13,r4
  76
  77   // Call C entry point
  78   LoadConstantToReg (FixedPcdGet32(PcdMemorySize) ,r1)    /* memory size arg1          */
  79   LoadConstantToReg (FixedPcdGet32(PcdMemoryBase) ,r0)    /* memory size arg0         */
  80   blx      ASM_PFX(CEntryPoint) /* Assume C code is thumb    */
  81
  82 ShouldNeverGetHere:
  83   /* _CEntryPoint should never return */
  84   b       ShouldNeverGetHere
  85