BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4 #
   5 # This program and the accompanying materials
   6 # are licensed and made available under the terms and conditions of the BSD License
   7 # which accompanies this distribution.  The full text of the license may be found at
   8 # http://opensource.org/licenses/bsd-license.php
   9 #
  10 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 #
  13 #------------------------------------------------------------------------------
  14
  15 #include <AsmMacroIoLib.h>
  16 #include <Library/PcdLib.h>
  17
  18 .text
  19 .align 3
  20
  21 .globl ASM_PFX(CEntryPoint)
  22 .globl ASM_PFX(_ModuleEntryPoint)
  23 INTERWORK_FUNC(_ModuleEntryPoint)
  24
  25 ASM_PFX(_ModuleEntryPoint):
  26
  27   //Disable L2 cache
  28   mrc     p15, 0, r0, c1, c0, 1   // read Auxiliary Control Register
  29   bic     r0, r0, #0x00000002     // disable L2 cache
  30   mcr     p15, 0, r0, c1, c0, 1   // store Auxiliary Control Register
  31
  32   //Enable Strict alignment checking & Instruction cache
  33   mrc     p15, 0, r0, c1, c0, 0
  34   bic     r0, r0, #0x00002300     /* clear bits 13, 9:8 (--V- --RS) */
  35   bic     r0, r0, #0x00000005     /* clear bits 0, 2 (---- -C-M) */
  36   orr     r0, r0, #0x00000002     /* set bit 1 (A) Align */
  37   orr     r0, r0, #0x00001000     /* set bit 12 (I) enable I-Cache */
  38   mcr     p15, 0, r0, c1, c0, 0
  39
  40   // Enable NEON register in case folks want to use them for optimizations (CopyMem)
  41   mrc     p15, 0, r0, c1, c0, 2
  42   orr     r0, r0, #0x00f00000   // Enable VPF access (V* instructions)
  43   mcr     p15, 0, r0, c1, c0, 2
  44   mov     r0, #0x40000000       // Set EN bit in FPEXC
  45   mcr     p10,#0x7,r0,c8,c0,#0  // msr     FPEXC,r0 in ARM assembly
  46
  47
  48   // Set CPU vectors to start of DRAM
  49   LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base
  50   mcr     p15, 0, r0, c12, c0, 0
  51   isb                               // Sync changes to control registers
  52
  53   // Fill vector table with branchs to current pc (jmp $)
  54   ldr     r1, ShouldNeverGetHere
  55   movs    r2, #0
  56 FillVectors:
  57   str     r1, [r0, r2]
  58   adds    r2, r2, #4
  59   cmp     r2, #32
  60   bne     FillVectors
  61
  62   /* before we call C code, lets setup the stack pointer in internal RAM */
  63 stack_pointer_setup:
  64
  65   //
  66   // Set stack based on PCD values. Need to do it this way to make C code work
  67   // when it runs from FLASH.
  68   //
  69   LoadConstantToReg (FixedPcdGet32(PcdPrePiStackBase) ,r2)    /* stack base arg2  */
  70   LoadConstantToReg (FixedPcdGet32(PcdPrePiStackSize) ,r3)    /* stack size arg3  */
  71   add     r4, r2, r3
  72
  73   //Enter SVC mode and set up SVC stack pointer
  74   mov     r0,#0x13|0x80|0x40
  75   msr     CPSR_c,r0
  76   mov     r13,r4
  77
  78   // Call C entry point
  79   LoadConstantToReg (FixedPcdGet32(PcdMemorySize) ,r1)    /* memory size arg1          */
  80   LoadConstantToReg (FixedPcdGet32(PcdMemoryBase) ,r0)    /* memory size arg0         */
  81   blx      ASM_PFX(CEntryPoint) /* Assume C code is thumb    */
  82
  83 ShouldNeverGetHere:
  84   /* _CEntryPoint should never return */
  85   b       ShouldNeverGetHere
  86