BeagleBoardPkg/Sec/Cache.c

   1 /** @file
   2
   3   Copyright (c) 2008-2009, Apple Inc. All rights reserved.
   4
   5   All rights reserved. This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #include <PiPei.h>
  16
  17 #include <Library/ArmLib.h>
  18 #include <Library/PrePiLib.h>
  19 #include <Library/PcdLib.h>
  20
  21 // DDR attributes
  22 #define DDR_ATTRIBUTES_CACHED                ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
  23 #define DDR_ATTRIBUTES_UNCACHED              ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
  24
  25 // SoC registers. L3 interconnects
  26 #define SOC_REGISTERS_L3_PHYSICAL_BASE       0x68000000
  27 #define SOC_REGISTERS_L3_PHYSICAL_LENGTH     0x08000000
  28 #define SOC_REGISTERS_L3_ATTRIBUTES          ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
  29
  30 // SoC registers. L4 interconnects
  31 #define SOC_REGISTERS_L4_PHYSICAL_BASE       0x48000000
  32 #define SOC_REGISTERS_L4_PHYSICAL_LENGTH     0x08000000
  33 #define SOC_REGISTERS_L4_ATTRIBUTES          ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
  34
  35 VOID
  36 InitCache (
  37   IN  UINT32  MemoryBase,
  38   IN  UINT32  MemoryLength
  39   )
  40 {
  41   UINTN                         UncachedMemoryMask;
  42   UINT32                        CacheAttributes;
  43   ARM_MEMORY_REGION_DESCRIPTOR  MemoryTable[5];
  44   VOID                          *TranslationTableBase;
  45   UINTN                         TranslationTableSize;
  46
  47   UncachedMemoryMask = PcdGet64(PcdArmUncachedMemoryMask);
  48
  49   if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
  50     CacheAttributes = DDR_ATTRIBUTES_CACHED;
  51   } else {
  52     CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
  53   }
  54
  55   // DDR
  56   MemoryTable[0].PhysicalBase = MemoryBase;
  57   MemoryTable[0].VirtualBase  = MemoryBase;
  58   MemoryTable[0].Length       = MemoryLength;
  59   MemoryTable[0].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;
  60
  61   // Uncached DDR Mirror
  62   MemoryTable[1].PhysicalBase = MemoryBase;
  63   MemoryTable[1].VirtualBase  = MemoryBase | UncachedMemoryMask;
  64   MemoryTable[1].Length       = MemoryLength;
  65   MemoryTable[1].Attributes   = DDR_ATTRIBUTES_UNCACHED;
  66
  67   // SOC Registers. L3 interconnects
  68   MemoryTable[2].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE;
  69   MemoryTable[2].VirtualBase  = SOC_REGISTERS_L3_PHYSICAL_BASE;
  70   MemoryTable[2].Length       = SOC_REGISTERS_L3_PHYSICAL_LENGTH;
  71   MemoryTable[2].Attributes   = SOC_REGISTERS_L3_ATTRIBUTES;
  72
  73   // SOC Registers. L4 interconnects
  74   MemoryTable[3].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE;
  75   MemoryTable[3].VirtualBase  = SOC_REGISTERS_L4_PHYSICAL_BASE;
  76   MemoryTable[3].Length       = SOC_REGISTERS_L4_PHYSICAL_LENGTH;
  77   MemoryTable[3].Attributes   = SOC_REGISTERS_L4_ATTRIBUTES;
  78
  79   // End of Table
  80   MemoryTable[4].PhysicalBase = 0;
  81   MemoryTable[4].VirtualBase  = 0;
  82   MemoryTable[4].Length       = 0;
  83   MemoryTable[4].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;
  84
  85   ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);
  86
  87   BuildMemoryAllocationHob((EFI_PHYSICAL_ADDRESS)(UINTN)TranslationTableBase, TranslationTableSize, EfiBootServicesData);
  88 }