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[mirror_edk2.git] / BeagleBoardPkg / Sec / PadConfiguration.c
1 /** @file
2
3 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
4
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #include <PiPei.h>
16 #include <Library/IoLib.h>
17 #include <Library/DebugLib.h>
18 #include <Omap3530/Omap3530.h>
19
20 #define NUM_PINS 238
21
22 PAD_CONFIGURATION PadConfigurationTable[NUM_PINS] = {
23 //Pin, MuxMode, PullConfig, InputEnable
24 { SDRC_D0, MUXMODE0, PULL_DISABLED, INPUT },
25 { SDRC_D1, MUXMODE0, PULL_DISABLED, INPUT },
26 { SDRC_D2, MUXMODE0, PULL_DISABLED, INPUT },
27 { SDRC_D3, MUXMODE0, PULL_DISABLED, INPUT },
28 { SDRC_D4, MUXMODE0, PULL_DISABLED, INPUT },
29 { SDRC_D5, MUXMODE0, PULL_DISABLED, INPUT },
30 { SDRC_D6, MUXMODE0, PULL_DISABLED, INPUT },
31 { SDRC_D7, MUXMODE0, PULL_DISABLED, INPUT },
32 { SDRC_D8, MUXMODE0, PULL_DISABLED, INPUT },
33 { SDRC_D9, MUXMODE0, PULL_DISABLED, INPUT },
34 { SDRC_D10, MUXMODE0, PULL_DISABLED, INPUT },
35 { SDRC_D11, MUXMODE0, PULL_DISABLED, INPUT },
36 { SDRC_D12, MUXMODE0, PULL_DISABLED, INPUT },
37 { SDRC_D13, MUXMODE0, PULL_DISABLED, INPUT },
38 { SDRC_D14, MUXMODE0, PULL_DISABLED, INPUT },
39 { SDRC_D15, MUXMODE0, PULL_DISABLED, INPUT },
40 { SDRC_D16, MUXMODE0, PULL_DISABLED, INPUT },
41 { SDRC_D17, MUXMODE0, PULL_DISABLED, INPUT },
42 { SDRC_D18, MUXMODE0, PULL_DISABLED, INPUT },
43 { SDRC_D19, MUXMODE0, PULL_DISABLED, INPUT },
44 { SDRC_D20, MUXMODE0, PULL_DISABLED, INPUT },
45 { SDRC_D21, MUXMODE0, PULL_DISABLED, INPUT },
46 { SDRC_D22, MUXMODE0, PULL_DISABLED, INPUT },
47 { SDRC_D23, MUXMODE0, PULL_DISABLED, INPUT },
48 { SDRC_D24, MUXMODE0, PULL_DISABLED, INPUT },
49 { SDRC_D25, MUXMODE0, PULL_DISABLED, INPUT },
50 { SDRC_D26, MUXMODE0, PULL_DISABLED, INPUT },
51 { SDRC_D27, MUXMODE0, PULL_DISABLED, INPUT },
52 { SDRC_D28, MUXMODE0, PULL_DISABLED, INPUT },
53 { SDRC_D29, MUXMODE0, PULL_DISABLED, INPUT },
54 { SDRC_D30, MUXMODE0, PULL_DISABLED, INPUT },
55 { SDRC_D31, MUXMODE0, PULL_DISABLED, INPUT },
56 { SDRC_CLK, MUXMODE0, PULL_DISABLED, INPUT },
57 { SDRC_DQS0, MUXMODE0, PULL_DISABLED, INPUT },
58 { SDRC_CKE0, MUXMODE0, PULL_UP_SELECTED, INPUT },
59 { SDRC_CKE1, MUXMODE7, PULL_DISABLED, INPUT },
60 { SDRC_DQS1, MUXMODE0, PULL_DISABLED, INPUT },
61 { SDRC_DQS2, MUXMODE0, PULL_DISABLED, INPUT },
62 { SDRC_DQS3, MUXMODE0, PULL_DISABLED, INPUT },
63 { GPMC_A1, MUXMODE0, PULL_DISABLED, OUTPUT },
64 { GPMC_A2, MUXMODE0, PULL_DISABLED, OUTPUT },
65 { GPMC_A3, MUXMODE0, PULL_DISABLED, OUTPUT },
66 { GPMC_A4, MUXMODE0, PULL_DISABLED, OUTPUT },
67 { GPMC_A5, MUXMODE0, PULL_DISABLED, OUTPUT },
68 { GPMC_A6, MUXMODE0, PULL_DISABLED, OUTPUT },
69 { GPMC_A7, MUXMODE0, PULL_DISABLED, OUTPUT },
70 { GPMC_A8, MUXMODE0, PULL_DISABLED, OUTPUT },
71 { GPMC_A9, MUXMODE0, PULL_DISABLED, OUTPUT },
72 { GPMC_A10, MUXMODE0, PULL_DISABLED, OUTPUT },
73 { GPMC_D0, MUXMODE0, PULL_DISABLED, INPUT },
74 { GPMC_D1, MUXMODE0, PULL_DISABLED, INPUT },
75 { GPMC_D2, MUXMODE0, PULL_DISABLED, INPUT },
76 { GPMC_D3, MUXMODE0, PULL_DISABLED, INPUT },
77 { GPMC_D4, MUXMODE0, PULL_DISABLED, INPUT },
78 { GPMC_D5, MUXMODE0, PULL_DISABLED, INPUT },
79 { GPMC_D6, MUXMODE0, PULL_DISABLED, INPUT },
80 { GPMC_D7, MUXMODE0, PULL_DISABLED, INPUT },
81 { GPMC_D8, MUXMODE0, PULL_DISABLED, INPUT },
82 { GPMC_D9, MUXMODE0, PULL_DISABLED, INPUT },
83 { GPMC_D10, MUXMODE0, PULL_DISABLED, INPUT },
84 { GPMC_D11, MUXMODE0, PULL_DISABLED, INPUT },
85 { GPMC_D12, MUXMODE0, PULL_DISABLED, INPUT },
86 { GPMC_D13, MUXMODE0, PULL_DISABLED, INPUT },
87 { GPMC_D14, MUXMODE0, PULL_DISABLED, INPUT },
88 { GPMC_D15, MUXMODE0, PULL_DISABLED, INPUT },
89 { GPMC_NCS0, MUXMODE0, PULL_DISABLED, INPUT },
90 { GPMC_NCS1, MUXMODE0, PULL_UP_SELECTED, OUTPUT },
91 { GPMC_NCS2, MUXMODE0, PULL_UP_SELECTED, OUTPUT },
92 { GPMC_NCS3, MUXMODE0, PULL_UP_SELECTED, OUTPUT },
93 { GPMC_NCS4, MUXMODE0, PULL_UP_SELECTED, OUTPUT },
94 { GPMC_NCS5, MUXMODE0, PULL_DISABLED, OUTPUT },
95 { GPMC_NCS6, MUXMODE1, PULL_DISABLED, INPUT },
96 { GPMC_NCS7, MUXMODE1, PULL_UP_SELECTED, INPUT },
97 { GPMC_CLK, MUXMODE0, PULL_DISABLED, OUTPUT },
98 { GPMC_NADV_ALE, MUXMODE0, PULL_DISABLED, INPUT },
99 { GPMC_NOE, MUXMODE0, PULL_DISABLED, INPUT },
100 { GPMC_NWE, MUXMODE0, PULL_DISABLED, INPUT },
101 { GPMC_NBE0_CLE, MUXMODE0, PULL_DISABLED, OUTPUT },
102 { GPMC_NBE1, MUXMODE0, PULL_DISABLED, INPUT },
103 { GPMC_NWP, MUXMODE0, PULL_DISABLED, INPUT },
104 { GPMC_WAIT0, MUXMODE0, PULL_UP_SELECTED, INPUT },
105 { GPMC_WAIT1, MUXMODE0, PULL_UP_SELECTED, INPUT },
106 { GPMC_WAIT2, MUXMODE0, PULL_UP_SELECTED, INPUT },
107 { GPMC_WAIT3, MUXMODE0, PULL_UP_SELECTED, INPUT },
108 { DSS_PCLK, MUXMODE0, PULL_DISABLED, OUTPUT },
109 { DSS_HSYNC, MUXMODE0, PULL_DISABLED, OUTPUT },
110 { DSS_PSYNC, MUXMODE0, PULL_DISABLED, OUTPUT },
111 { DSS_ACBIAS, MUXMODE0, PULL_DISABLED, OUTPUT },
112 { DSS_DATA0, MUXMODE0, PULL_DISABLED, OUTPUT },
113 { DSS_DATA1, MUXMODE0, PULL_DISABLED, OUTPUT },
114 { DSS_DATA2, MUXMODE0, PULL_DISABLED, OUTPUT },
115 { DSS_DATA3, MUXMODE0, PULL_DISABLED, OUTPUT },
116 { DSS_DATA4, MUXMODE0, PULL_DISABLED, OUTPUT },
117 { DSS_DATA5, MUXMODE0, PULL_DISABLED, OUTPUT },
118 { DSS_DATA6, MUXMODE0, PULL_DISABLED, OUTPUT },
119 { DSS_DATA7, MUXMODE0, PULL_DISABLED, OUTPUT },
120 { DSS_DATA8, MUXMODE0, PULL_DISABLED, OUTPUT },
121 { DSS_DATA9, MUXMODE0, PULL_DISABLED, OUTPUT },
122 { DSS_DATA10, MUXMODE0, PULL_DISABLED, OUTPUT },
123 { DSS_DATA11, MUXMODE0, PULL_DISABLED, OUTPUT },
124 { DSS_DATA12, MUXMODE0, PULL_DISABLED, OUTPUT },
125 { DSS_DATA13, MUXMODE0, PULL_DISABLED, OUTPUT },
126 { DSS_DATA14, MUXMODE0, PULL_DISABLED, OUTPUT },
127 { DSS_DATA15, MUXMODE0, PULL_DISABLED, OUTPUT },
128 { DSS_DATA16, MUXMODE0, PULL_DISABLED, OUTPUT },
129 { DSS_DATA17, MUXMODE0, PULL_DISABLED, OUTPUT },
130 { DSS_DATA18, MUXMODE0, PULL_DISABLED, OUTPUT },
131 { DSS_DATA19, MUXMODE0, PULL_DISABLED, OUTPUT },
132 { DSS_DATA20, MUXMODE0, PULL_DISABLED, OUTPUT },
133 { DSS_DATA21, MUXMODE0, PULL_DISABLED, OUTPUT },
134 { DSS_DATA22, MUXMODE0, PULL_DISABLED, OUTPUT },
135 { DSS_DATA23, MUXMODE0, PULL_DISABLED, OUTPUT },
136 { CAM_HS, MUXMODE0, PULL_UP_SELECTED, INPUT },
137 { CAM_VS, MUXMODE0, PULL_UP_SELECTED, INPUT },
138 { CAM_XCLKA, MUXMODE0, PULL_DISABLED, OUTPUT },
139 { CAM_PCLK, MUXMODE0, PULL_UP_SELECTED, INPUT },
140 { CAM_FLD, MUXMODE4, PULL_DISABLED, OUTPUT },
141 { CAM_D0, MUXMODE0, PULL_DISABLED, INPUT },
142 { CAM_D1, MUXMODE0, PULL_DISABLED, INPUT },
143 { CAM_D2, MUXMODE0, PULL_DISABLED, INPUT },
144 { CAM_D3, MUXMODE0, PULL_DISABLED, INPUT },
145 { CAM_D4, MUXMODE0, PULL_DISABLED, INPUT },
146 { CAM_D5, MUXMODE0, PULL_DISABLED, INPUT },
147 { CAM_D6, MUXMODE0, PULL_DISABLED, INPUT },
148 { CAM_D7, MUXMODE0, PULL_DISABLED, INPUT },
149 { CAM_D8, MUXMODE0, PULL_DISABLED, INPUT },
150 { CAM_D9, MUXMODE0, PULL_DISABLED, INPUT },
151 { CAM_D10, MUXMODE0, PULL_DISABLED, INPUT },
152 { CAM_D11, MUXMODE0, PULL_DISABLED, INPUT },
153 { CAM_XCLKB, MUXMODE0, PULL_DISABLED, OUTPUT },
154 { CAM_WEN, MUXMODE4, PULL_DISABLED, INPUT },
155 { CAM_STROBE, MUXMODE0, PULL_DISABLED, OUTPUT },
156 { CSI2_DX0, MUXMODE0, PULL_DISABLED, INPUT },
157 { CSI2_DY0, MUXMODE0, PULL_DISABLED, INPUT },
158 { CSI2_DX1, MUXMODE0, PULL_DISABLED, INPUT },
159 { CSI2_DY1, MUXMODE0, PULL_DISABLED, INPUT },
160 { MCBSP2_FSX, MUXMODE0, PULL_DISABLED, INPUT },
161 { MCBSP2_CLKX, MUXMODE0, PULL_DISABLED, INPUT },
162 { MCBSP2_DR, MUXMODE0, PULL_DISABLED, INPUT },
163 { MCBSP2_DX, MUXMODE0, PULL_DISABLED, OUTPUT },
164 { MMC1_CLK, MUXMODE0, PULL_UP_SELECTED, OUTPUT },
165 { MMC1_CMD, MUXMODE0, PULL_UP_SELECTED, INPUT },
166 { MMC1_DAT0, MUXMODE0, PULL_UP_SELECTED, INPUT },
167 { MMC1_DAT1, MUXMODE0, PULL_UP_SELECTED, INPUT },
168 { MMC1_DAT2, MUXMODE0, PULL_UP_SELECTED, INPUT },
169 { MMC1_DAT3, MUXMODE0, PULL_UP_SELECTED, INPUT },
170 { MMC1_DAT4, MUXMODE0, PULL_UP_SELECTED, INPUT },
171 { MMC1_DAT5, MUXMODE0, PULL_UP_SELECTED, INPUT },
172 { MMC1_DAT6, MUXMODE0, PULL_UP_SELECTED, INPUT },
173 { MMC1_DAT7, MUXMODE0, PULL_UP_SELECTED, INPUT },
174 { MMC2_CLK, MUXMODE4, PULL_UP_SELECTED, INPUT },
175 { MMC2_CMD, MUXMODE4, PULL_UP_SELECTED, INPUT },
176 { MMC2_DAT0, MUXMODE4, PULL_UP_SELECTED, INPUT },
177 { MMC2_DAT1, MUXMODE4, PULL_UP_SELECTED, INPUT },
178 { MMC2_DAT2, MUXMODE4, PULL_UP_SELECTED, INPUT },
179 { MMC2_DAT3, MUXMODE4, PULL_UP_SELECTED, INPUT },
180 { MMC2_DAT4, MUXMODE4, PULL_UP_SELECTED, INPUT },
181 { MMC2_DAT5, MUXMODE4, PULL_UP_SELECTED, INPUT },
182 { MMC2_DAT6, MUXMODE4, PULL_UP_SELECTED, INPUT },
183 { MMC2_DAT7, MUXMODE4, PULL_UP_SELECTED, INPUT },
184 { MCBSP3_DX, MUXMODE4, PULL_DISABLED, OUTPUT },
185 { MCBSP3_DR, MUXMODE4, PULL_DISABLED, OUTPUT },
186 { MCBSP3_CLKX, MUXMODE4, PULL_DISABLED, OUTPUT },
187 { MCBSP3_FSX, MUXMODE4, PULL_DISABLED, OUTPUT },
188 { UART2_CTS, MUXMODE0, PULL_UP_SELECTED, INPUT },
189 { UART2_RTS, MUXMODE0, PULL_DISABLED, OUTPUT },
190 { UART2_TX, MUXMODE0, PULL_DISABLED, OUTPUT },
191 { UART2_RX, MUXMODE4, PULL_DISABLED, OUTPUT },
192 { UART1_TX, MUXMODE0, PULL_DISABLED, OUTPUT },
193 { UART1_RTS, MUXMODE4, PULL_DISABLED, OUTPUT },
194 { UART1_CTS, MUXMODE4, PULL_DISABLED, OUTPUT },
195 { UART1_RX, MUXMODE0, PULL_DISABLED, INPUT },
196 { MCBSP4_CLKX, MUXMODE1, PULL_DISABLED, INPUT },
197 { MCBSP4_DR, MUXMODE1, PULL_DISABLED, INPUT },
198 { MCBSP4_DX, MUXMODE1, PULL_DISABLED, INPUT },
199 { MCBSP4_FSX, MUXMODE1, PULL_DISABLED, INPUT },
200 { MCBSP1_CLKR, MUXMODE4, PULL_DISABLED, OUTPUT },
201 { MCBSP1_FSR, MUXMODE4, PULL_UP_SELECTED, OUTPUT },
202 { MCBSP1_DX, MUXMODE4, PULL_DISABLED, OUTPUT },
203 { MCBSP1_DR, MUXMODE4, PULL_DISABLED, OUTPUT },
204 { MCBSP1_CLKS, MUXMODE0, PULL_UP_SELECTED, INPUT },
205 { MCBSP1_FSX, MUXMODE4, PULL_DISABLED, OUTPUT },
206 { MCBSP1_CLKX, MUXMODE4, PULL_DISABLED, OUTPUT },
207 { UART3_CTS_RCTX,MUXMODE0, PULL_UP_SELECTED, INPUT },
208 { UART3_RTS_SD, MUXMODE0, PULL_DISABLED, OUTPUT },
209 { UART3_RX_IRRX, MUXMODE0, PULL_DISABLED, INPUT },
210 { UART3_TX_IRTX, MUXMODE0, PULL_DISABLED, OUTPUT },
211 { HSUSB0_CLK, MUXMODE0, PULL_DISABLED, INPUT },
212 { HSUSB0_STP, MUXMODE0, PULL_UP_SELECTED, OUTPUT },
213 { HSUSB0_DIR, MUXMODE0, PULL_DISABLED, INPUT },
214 { HSUSB0_NXT, MUXMODE0, PULL_DISABLED, INPUT },
215 { HSUSB0_DATA0, MUXMODE0, PULL_DISABLED, INPUT },
216 { HSUSB0_DATA1, MUXMODE0, PULL_DISABLED, INPUT },
217 { HSUSB0_DATA2, MUXMODE0, PULL_DISABLED, INPUT },
218 { HSUSB0_DATA3, MUXMODE0, PULL_DISABLED, INPUT },
219 { HSUSB0_DATA4, MUXMODE0, PULL_DISABLED, INPUT },
220 { HSUSB0_DATA5, MUXMODE0, PULL_DISABLED, INPUT },
221 { HSUSB0_DATA6, MUXMODE0, PULL_DISABLED, INPUT },
222 { HSUSB0_DATA7, MUXMODE0, PULL_DISABLED, INPUT },
223 { I2C1_SCL, MUXMODE0, PULL_UP_SELECTED, INPUT },
224 { I2C1_SDA, MUXMODE0, PULL_UP_SELECTED, INPUT },
225 { I2C2_SCL, MUXMODE4, PULL_UP_SELECTED, INPUT },
226 { I2C2_SDA, MUXMODE4, PULL_UP_SELECTED, INPUT },
227 { I2C3_SCL, MUXMODE0, PULL_UP_SELECTED, INPUT },
228 { I2C3_SDA, MUXMODE0, PULL_UP_SELECTED, INPUT },
229 { HDQ_SIO, MUXMODE4, PULL_UP_SELECTED, OUTPUT },
230 { MCSPI1_CLK, MUXMODE4, PULL_UP_SELECTED, INPUT },
231 { MCSPI1_SIMO, MUXMODE4, PULL_UP_SELECTED, INPUT },
232 { MCSPI1_SOMI, MUXMODE0, PULL_DISABLED, INPUT },
233 { MCSPI1_CS0, MUXMODE0, PULL_UP_SELECTED, INPUT },
234 { MCSPI1_CS1, MUXMODE0, PULL_UP_SELECTED, OUTPUT },
235 { MCSPI1_CS2, MUXMODE4, PULL_DISABLED, OUTPUT },
236 { MCSPI1_CS3, MUXMODE3, PULL_UP_SELECTED, INPUT },
237 { MCSPI2_CLK, MUXMODE3, PULL_UP_SELECTED, INPUT },
238 { MCSPI2_SIMO, MUXMODE3, PULL_UP_SELECTED, INPUT },
239 { MCSPI2_SOMI, MUXMODE3, PULL_UP_SELECTED, INPUT },
240 { MCSPI2_CS0, MUXMODE3, PULL_UP_SELECTED, INPUT },
241 { MCSPI2_CS1, MUXMODE3, PULL_UP_SELECTED, INPUT },
242 { SYS_NIRQ, MUXMODE0, PULL_UP_SELECTED, INPUT },
243 { SYS_CLKOUT2, MUXMODE4, PULL_UP_SELECTED, INPUT },
244 { ETK_CLK, MUXMODE3, PULL_UP_SELECTED, OUTPUT },
245 { ETK_CTL, MUXMODE3, PULL_UP_SELECTED, OUTPUT },
246 { ETK_D0, MUXMODE3, PULL_UP_SELECTED, INPUT },
247 { ETK_D1, MUXMODE3, PULL_UP_SELECTED, INPUT },
248 { ETK_D2, MUXMODE3, PULL_UP_SELECTED, INPUT },
249 { ETK_D3, MUXMODE3, PULL_UP_SELECTED, INPUT },
250 { ETK_D4, MUXMODE3, PULL_UP_SELECTED, INPUT },
251 { ETK_D5, MUXMODE3, PULL_UP_SELECTED, INPUT },
252 { ETK_D6, MUXMODE3, PULL_UP_SELECTED, INPUT },
253 { ETK_D7, MUXMODE3, PULL_UP_SELECTED, INPUT },
254 { ETK_D8, MUXMODE3, PULL_UP_SELECTED, INPUT },
255 { ETK_D9, MUXMODE4, PULL_UP_SELECTED, INPUT },
256 { ETK_D10, MUXMODE3, PULL_UP_SELECTED, OUTPUT },
257 { ETK_D11, MUXMODE3, PULL_UP_SELECTED, OUTPUT },
258 { ETK_D12, MUXMODE3, PULL_UP_SELECTED, INPUT },
259 { ETK_D13, MUXMODE3, PULL_UP_SELECTED, INPUT },
260 { ETK_D14, MUXMODE3, PULL_UP_SELECTED, INPUT },
261 { ETK_D15, MUXMODE3, PULL_UP_SELECTED, INPUT }
262 };
263
264 VOID
265 PadConfiguration (
266 VOID
267 )
268 {
269 UINTN Index;
270 UINT16 PadConfiguration;
271 UINTN NumPinsToConfigure = sizeof(PadConfigurationTable)/sizeof(PAD_CONFIGURATION);
272
273 for (Index = 0; Index < NumPinsToConfigure; Index++) {
274 //Set up Pad configuration for particular pin.
275 PadConfiguration = (PadConfigurationTable[Index].MuxMode << MUXMODE_OFFSET);
276 PadConfiguration |= (PadConfigurationTable[Index].PullConfig << PULL_CONFIG_OFFSET);
277 PadConfiguration |= (PadConfigurationTable[Index].InputEnable << INPUTENABLE_OFFSET);
278
279 //Configure the pin with specific Pad configuration.
280 MmioWrite16(PadConfigurationTable[Index].Pin, PadConfiguration);
281 }
282 }
EFI Development Kit II mirror for PVE