BeagleBoardPkg/Sec/Sec.c

   1 /** @file
   2   C Entry point for the SEC. First C code after the reset vector.
   3
   4   Copyright (c) 2008-2009, Apple Inc. All rights reserved.
   5
   6   All rights reserved. This program and the accompanying materials
   7   are licensed and made available under the terms and conditions of the BSD License
   8   which accompanies this distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #include <PiPei.h>
  17
  18 #include <Library/DebugLib.h>
  19 #include <Library/PrePiLib.h>
  20 #include <Library/PcdLib.h>
  21 #include <Library/IoLib.h>
  22 #include <Library/OmapLib.h>
  23 #include <Library/ArmLib.h>
  24 #include <Library/PeCoffGetEntryPointLib.h>
  25
  26 #include <Ppi/GuidedSectionExtraction.h>
  27
  28 #include <Omap3530/Omap3530.h>
  29
  30 VOID
  31 EFIAPI
  32 _ModuleEntryPoint(
  33   VOID
  34   );
  35
  36 CHAR8 *
  37 DeCygwinPathIfNeeded (
  38   IN  CHAR8   *Name
  39   );
  40
  41 VOID
  42 PadConfiguration (
  43   VOID
  44   );
  45
  46 VOID
  47 ClockInit (
  48   VOID
  49   );
  50
  51 VOID
  52 TimerInit (
  53   VOID
  54   )
  55 {
  56   UINTN  Timer            = FixedPcdGet32(PcdBeagleFreeTimer);
  57   UINT32 TimerBaseAddress = TimerBase(Timer);
  58
  59   // Set source clock for GPT3 & GPT4 to SYS_CLK
  60   MmioOr32(CM_CLKSEL_PER, CM_CLKSEL_PER_CLKSEL_GPT3_SYS
  61                           | CM_CLKSEL_PER_CLKSEL_GPT4_SYS);
  62
  63   // Set count & reload registers
  64   MmioWrite32(TimerBaseAddress + GPTIMER_TCRR, 0x00000000);
  65   MmioWrite32(TimerBaseAddress + GPTIMER_TLDR, 0x00000000);
  66
  67   // Disable interrupts
  68   MmioWrite32(TimerBaseAddress + GPTIMER_TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_DISABLE | TIER_MAT_IT_DISABLE);
  69
  70   // Start Timer
  71   MmioWrite32(TimerBaseAddress + GPTIMER_TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);
  72
  73   //Disable OMAP Watchdog timer (WDT2)
  74   MmioWrite32(WDTIMER2_BASE + WSPR, 0xAAAA);
  75   DEBUG ((EFI_D_ERROR, "Magic delay to disable watchdog timers properly.\n"));
  76   MmioWrite32(WDTIMER2_BASE + WSPR, 0x5555);
  77 }
  78
  79 VOID
  80 UartInit (
  81   VOID
  82   )
  83 {
  84   UINTN   Uart            = FixedPcdGet32(PcdBeagleConsoleUart);
  85   UINT32  UartBaseAddress = UartBase(Uart);
  86
  87   // Set MODE_SELECT=DISABLE before trying to initialize or modify DLL, DLH registers.
  88   MmioWrite32(UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_DISABLE);
  89
  90   // Put device in configuration mode.
  91   MmioWrite32(UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_ENABLE);
  92
  93   // Programmable divisor N = 48Mhz/16/115200 = 26
  94   MmioWrite32(UartBaseAddress + UART_DLL_REG, 26); // low divisor
  95   MmioWrite32(UartBaseAddress + UART_DLH_REG,  0); // high divisor
  96
  97   // Enter into UART operational mode.
  98   MmioWrite32(UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_DISABLE | UART_LCR_CHAR_LENGTH_8);
  99
 100   // Force DTR and RTS output to active
 101   MmioWrite32(UartBaseAddress + UART_MCR_REG, UART_MCR_RTS_FORCE_ACTIVE | UART_MCR_DTR_FORCE_ACTIVE);
 102
 103   // Clear & enable fifos
 104   MmioWrite32(UartBaseAddress + UART_FCR_REG, UART_FCR_TX_FIFO_CLEAR | UART_FCR_RX_FIFO_CLEAR | UART_FCR_FIFO_ENABLE);
 105
 106   // Restore MODE_SELECT
 107   MmioWrite32(UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_UART_16X);
 108 }
 109
 110 VOID
 111 InitCache (
 112   IN  UINT32  MemoryBase,
 113   IN  UINT32  MemoryLength
 114   );
 115
 116 EFI_STATUS
 117 EFIAPI
 118 ExtractGuidedSectionLibConstructor (
 119   VOID
 120   );
 121
 122 EFI_STATUS
 123 EFIAPI
 124 LzmaDecompressLibConstructor (
 125   VOID
 126   );
 127
 128 /**
 129   If the build is done on cygwin the paths are cygpaths.
 130   /cygdrive/c/tmp.txt vs c:\tmp.txt so we need to convert
 131   them to work with RVD commands
 132
 133   This is just code to help print out RVD symbol load command.
 134   If you build with cygwin paths aren't compatible with RVD.
 135
 136   @param  Name  Path to convert if needed
 137
 138 **/
 139 CHAR8 *
 140 SecDeCygwinPathIfNeeded (
 141   IN  CHAR8   *Name
 142   )
 143 {
 144   CHAR8   *Ptr;
 145   UINTN   Index;
 146   UINTN   Len;
 147
 148   Ptr = AsciiStrStr (Name, "/cygdrive/");
 149   if (Ptr == NULL) {
 150     return Name;
 151   }
 152
 153   Len = AsciiStrLen (Ptr);
 154
 155   // convert "/cygdrive" to spaces
 156   for (Index = 0; Index < 9; Index++) {
 157     Ptr[Index] = ' ';
 158   }
 159
 160   // convert /c to c:
 161   Ptr[9]  = Ptr[10];
 162   Ptr[10] = ':';
 163
 164   // switch path seperators
 165   for (Index = 11; Index < Len; Index++) {
 166     if (Ptr[Index] == '/') {
 167       Ptr[Index] = '\\' ;
 168     }
 169   }
 170
 171   return Name;
 172 }
 173
 174
 175 VOID
 176 CEntryPoint (
 177   IN  VOID  *MemoryBase,
 178   IN  UINTN MemorySize,
 179   IN  VOID  *StackBase,
 180   IN  UINTN StackSize
 181   )
 182 {
 183   VOID *HobBase;
 184
 185   //Set up Pin muxing.
 186   PadConfiguration();
 187
 188   // Set up system clocking
 189   ClockInit();
 190
 191   // Build a basic HOB list
 192   HobBase      = (VOID *)(UINTN)(FixedPcdGet32(PcdEmbeddedFdBaseAddress) + FixedPcdGet32(PcdEmbeddedFdSize));
 193   CreateHobList(MemoryBase, MemorySize, HobBase, StackBase);
 194
 195   // Enable program flow prediction, if supported.
 196   ArmEnableBranchPrediction();
 197
 198   // Initialize CPU cache
 199   InitCache((UINT32)MemoryBase, (UINT32)MemorySize);
 200
 201   // Add memory allocation hob for relocated FD
 202   BuildMemoryAllocationHob(FixedPcdGet32(PcdEmbeddedFdBaseAddress), FixedPcdGet32(PcdEmbeddedFdSize), EfiBootServicesData);
 203
 204   // Add the FVs to the hob list
 205   BuildFvHob(PcdGet32(PcdFlashFvMainBase), PcdGet32(PcdFlashFvMainSize));
 206
 207   // Start talking
 208   UartInit();
 209   DEBUG((EFI_D_ERROR, "UART Enabled\n"));
 210
 211   DEBUG_CODE_BEGIN ();
 212     //
 213     // On a debug build print out information about the SEC. This is really info about
 214     // the PE/COFF file we are currently running from. Useful for loading symbols in a
 215     // debugger. Remember our image is really part of the FV.
 216     //
 217     RETURN_STATUS       Status;
 218     EFI_PEI_FV_HANDLE   VolumeHandle;
 219     EFI_PEI_FILE_HANDLE FileHandle;
 220     VOID                *PeCoffImage;
 221     UINT32              Offset;
 222     CHAR8               *FilePath;
 223
 224     FfsAnyFvFindFirstFile (EFI_FV_FILETYPE_SECURITY_CORE, &VolumeHandle, &FileHandle);
 225     Status = FfsFindSectionData (EFI_SECTION_TE, FileHandle, &PeCoffImage);
 226     if (EFI_ERROR (Status)) {
 227       // Usually is a TE (PI striped down PE/COFF), but could be a full PE/COFF
 228       Status = FfsFindSectionData (EFI_SECTION_PE32, FileHandle, &PeCoffImage);
 229     }
 230     if (!EFI_ERROR (Status)) {
 231       Offset = PeCoffGetSizeOfHeaders (PeCoffImage);
 232       FilePath = PeCoffLoaderGetPdbPointer (PeCoffImage);
 233       if (FilePath != NULL) {
 234
 235         //
 236         // In general you should never have to use #ifdef __CC_ARM in the code. It
 237         // is hidden in the away in the MdePkg. But here we would like to print differnt things
 238         // for different toolchains.
 239         //
 240 #ifdef __CC_ARM
 241         // Print out the command for the RVD debugger to load symbols for this image
 242         DEBUG ((EFI_D_ERROR, "load /a /ni /np %a &0x%08x\n", SecDeCygwinPathIfNeeded (FilePath), (CHAR8 *)PeCoffImage + Offset));
 243 #elif __GNUC__
 244         // This may not work correctly if you generate PE/COFF directlyas then the Offset would not be required
 245         DEBUG ((EFI_D_ERROR, "add-symbol-file %a 0x%08x\n", FilePath, PeCoffImage + Offset));
 246 #else
 247         DEBUG ((EFI_D_ERROR, "SEC starts at 0x%08x with an entry point at 0x%08x %a\n", PeCoffImage, _ModuleEntryPoint, FilePath));
 248 #endif
 249       }
 250     }
 251
 252    DEBUG_CODE_END ();
 253
 254
 255
 256   // Start up a free running time so that the timer lib will work
 257   TimerInit();
 258
 259   // SEC phase needs to run library constructors by hand.
 260   ExtractGuidedSectionLibConstructor();
 261   LzmaDecompressLibConstructor();
 262
 263   DecompressFirstFv ();
 264
 265   // Load the DXE Core and transfer control to it
 266   LoadDxeCoreFromFv(NULL, 0);
 267
 268   // DXE Core should always load and never return
 269   ASSERT(FALSE);
 270 }
 271