CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c

   1 /** @file
   2   Scan the entire PCI bus for root bridges to support coreboot UEFI payload.
   3
   4   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
   5
   6   This program and the accompanying materials are licensed and made available
   7   under the terms and conditions of the BSD License which accompanies this
   8   distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php.
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
  12   WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #include <PiDxe.h>
  17 #include <IndustryStandard/Pci.h>
  18 #include <Protocol/PciHostBridgeResourceAllocation.h>
  19 #include <Protocol/PciRootBridgeIo.h>
  20 #include <Library/BaseMemoryLib.h>
  21 #include <Library/DebugLib.h>
  22 #include <Library/MemoryAllocationLib.h>
  23 #include <Library/PciHostBridgeLib.h>
  24 #include <Library/PciLib.h>
  25 #include "PciHostBridge.h"
  26
  27 /**
  28   Adjust the collected PCI resource.
  29
  30   @param[in]  Io               IO aperture.
  31
  32   @param[in]  Mem              MMIO aperture.
  33
  34   @param[in]  MemAbove4G       MMIO aperture above 4G.
  35
  36   @param[in]  PMem             Prefetchable MMIO aperture.
  37
  38   @param[in]  PMemAbove4G      Prefetchable MMIO aperture above 4G.
  39 **/
  40 VOID
  41 AdjustRootBridgeResource (
  42   IN  PCI_ROOT_BRIDGE_APERTURE *Io,
  43   IN  PCI_ROOT_BRIDGE_APERTURE *Mem,
  44   IN  PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,
  45   IN  PCI_ROOT_BRIDGE_APERTURE *PMem,
  46   IN  PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G
  47 )
  48 {
  49   UINT64  Mask;
  50
  51   //
  52   // For now try to downgrade everything into MEM32 since
  53   // - coreboot does not assign resource above 4GB
  54   // - coreboot might allocate interleaved MEM32 and PMEM32 resource
  55   //   in some cases
  56   //
  57   if (PMem->Base < Mem->Base) {
  58     Mem->Base = PMem->Base;
  59   }
  60
  61   if (PMem->Limit > Mem->Limit) {
  62     Mem->Limit = PMem->Limit;
  63   }
  64
  65   PMem->Base  = MAX_UINT64;
  66   PMem->Limit = 0;
  67
  68   if (MemAbove4G->Base < 0x100000000ULL) {
  69     if (MemAbove4G->Base < Mem->Base) {
  70       Mem->Base  = MemAbove4G->Base;
  71     }
  72     if (MemAbove4G->Limit > Mem->Limit) {
  73       Mem->Limit = MemAbove4G->Limit;
  74     }
  75     MemAbove4G->Base  = MAX_UINT64;
  76     MemAbove4G->Limit = 0;
  77   }
  78
  79   if (PMemAbove4G->Base < 0x100000000ULL) {
  80     if (PMemAbove4G->Base < Mem->Base) {
  81       Mem->Base  = PMemAbove4G->Base;
  82     }
  83     if (PMemAbove4G->Limit > Mem->Limit) {
  84       Mem->Limit = PMemAbove4G->Limit;
  85     }
  86     PMemAbove4G->Base  = MAX_UINT64;
  87     PMemAbove4G->Limit = 0;
  88   }
  89
  90   //
  91   // Align IO  resource at 4K  boundary
  92   //
  93   Mask        = 0xFFFULL;
  94   Io->Limit   = (Io->Limit + Mask) & ~Mask;
  95   if (Io->Base != MAX_UINT64) {
  96     Io->Base &= ~Mask;
  97   }
  98
  99   //
 100   // Align MEM resource at 1MB boundary
 101   //
 102   Mask        = 0xFFFFFULL;
 103   Mem->Limit  = (Mem->Limit + Mask) & ~Mask;
 104   if (Mem->Base != MAX_UINT64) {
 105     Mem->Base &= ~Mask;
 106   }
 107 }
 108
 109 /**
 110   Probe a bar is existed or not.
 111
 112   @param[in]    Address           PCI address for the BAR.
 113   @param[out]   OriginalValue     The original bar value returned.
 114   @param[out]   Value             The probed bar value returned.
 115 **/
 116 STATIC
 117 VOID
 118 PcatPciRootBridgeBarExisted (
 119   IN  UINT64                         Address,
 120   OUT UINT32                         *OriginalValue,
 121   OUT UINT32                         *Value
 122 )
 123 {
 124   UINTN   PciAddress;
 125
 126   PciAddress = (UINTN)Address;
 127
 128   //
 129   // Preserve the original value
 130   //
 131   *OriginalValue = PciRead32 (PciAddress);
 132
 133   //
 134   // Disable timer interrupt while the BAR is probed
 135   //
 136   DisableInterrupts ();
 137
 138   PciWrite32 (PciAddress, 0xFFFFFFFF);
 139   *Value = PciRead32 (PciAddress);
 140   PciWrite32 (PciAddress, *OriginalValue);
 141
 142   //
 143   // Enable interrupt
 144   //
 145   EnableInterrupts ();
 146 }
 147
 148 /**
 149   Parse PCI bar and collect the assigned PCI resouce information.
 150
 151   @param[in]  Command          Supported attributes.
 152
 153   @param[in]  Bus              PCI bus number.
 154
 155   @param[in]  Device           PCI device number.
 156
 157   @param[in]  Function         PCI function number.
 158
 159   @param[in]  BarOffsetBase    PCI bar start offset.
 160
 161   @param[in]  BarOffsetEnd     PCI bar end offset.
 162
 163   @param[in]  Io               IO aperture.
 164
 165   @param[in]  Mem              MMIO aperture.
 166
 167   @param[in]  MemAbove4G       MMIO aperture above 4G.
 168
 169   @param[in]  PMem             Prefetchable MMIO aperture.
 170
 171   @param[in]  PMemAbove4G      Prefetchable MMIO aperture above 4G.
 172 **/
 173 STATIC
 174 VOID
 175 PcatPciRootBridgeParseBars (
 176   IN UINT16                         Command,
 177   IN UINTN                          Bus,
 178   IN UINTN                          Device,
 179   IN UINTN                          Function,
 180   IN UINTN                          BarOffsetBase,
 181   IN UINTN                          BarOffsetEnd,
 182   IN PCI_ROOT_BRIDGE_APERTURE       *Io,
 183   IN PCI_ROOT_BRIDGE_APERTURE       *Mem,
 184   IN PCI_ROOT_BRIDGE_APERTURE       *MemAbove4G,
 185   IN PCI_ROOT_BRIDGE_APERTURE       *PMem,
 186   IN PCI_ROOT_BRIDGE_APERTURE       *PMemAbove4G
 187
 188 )
 189 {
 190   UINT32                            OriginalValue;
 191   UINT32                            Value;
 192   UINT32                            OriginalUpperValue;
 193   UINT32                            UpperValue;
 194   UINT64                            Mask;
 195   UINTN                             Offset;
 196   UINT64                            Base;
 197   UINT64                            Length;
 198   UINT64                            Limit;
 199   PCI_ROOT_BRIDGE_APERTURE          *MemAperture;
 200
 201   for (Offset = BarOffsetBase; Offset < BarOffsetEnd; Offset += sizeof (UINT32)) {
 202     PcatPciRootBridgeBarExisted (
 203       PCI_LIB_ADDRESS (Bus, Device, Function, Offset),
 204       &OriginalValue, &Value
 205     );
 206     if (Value == 0) {
 207       continue;
 208     }
 209     if ((Value & BIT0) == BIT0) {
 210       //
 211       // IO Bar
 212       //
 213       if (Command & EFI_PCI_COMMAND_IO_SPACE) {
 214         Mask = 0xfffffffc;
 215         Base = OriginalValue & Mask;
 216         Length = ((~(Value & Mask)) & Mask) + 0x04;
 217         if (!(Value & 0xFFFF0000)) {
 218           Length &= 0x0000FFFF;
 219         }
 220         Limit = Base + Length - 1;
 221
 222         if ((Base > 0) && (Base < Limit)) {
 223           if (Io->Base > Base) {
 224             Io->Base = Base;
 225           }
 226           if (Io->Limit < Limit) {
 227             Io->Limit = Limit;
 228           }
 229         }
 230       }
 231     } else {
 232       //
 233       // Mem Bar
 234       //
 235       if (Command & EFI_PCI_COMMAND_MEMORY_SPACE) {
 236
 237         Mask = 0xfffffff0;
 238         Base = OriginalValue & Mask;
 239         Length = Value & Mask;
 240
 241         if ((Value & (BIT1 | BIT2)) == 0) {
 242           //
 243           // 32bit
 244           //
 245           Length = ((~Length) + 1) & 0xffffffff;
 246
 247           if ((Value & BIT3) == BIT3) {
 248             MemAperture = PMem;
 249           } else {
 250             MemAperture = Mem;
 251           }
 252         } else {
 253           //
 254           // 64bit
 255           //
 256           Offset += 4;
 257           PcatPciRootBridgeBarExisted (
 258             PCI_LIB_ADDRESS (Bus, Device, Function, Offset),
 259             &OriginalUpperValue,
 260             &UpperValue
 261           );
 262
 263           Base = Base | LShiftU64 ((UINT64) OriginalUpperValue, 32);
 264           Length = Length | LShiftU64 ((UINT64) UpperValue, 32);
 265           Length = (~Length) + 1;
 266
 267           if ((Value & BIT3) == BIT3) {
 268             MemAperture = PMemAbove4G;
 269           } else {
 270             MemAperture = MemAbove4G;
 271           }
 272         }
 273
 274         Limit = Base + Length - 1;
 275         if ((Base > 0) && (Base < Limit)) {
 276           if (MemAperture->Base > Base) {
 277             MemAperture->Base = Base;
 278           }
 279           if (MemAperture->Limit < Limit) {
 280             MemAperture->Limit = Limit;
 281           }
 282         }
 283       }
 284     }
 285   }
 286 }
 287
 288 /**
 289   Scan for all root bridges in platform.
 290
 291   @param[out] NumberOfRootBridges  Number of root bridges detected
 292
 293   @retval     Pointer to the allocated PCI_ROOT_BRIDGE structure array.
 294 **/
 295 PCI_ROOT_BRIDGE *
 296 ScanForRootBridges (
 297   OUT UINTN      *NumberOfRootBridges
 298 )
 299 {
 300   UINTN      PrimaryBus;
 301   UINTN      SubBus;
 302   UINT8      Device;
 303   UINT8      Function;
 304   UINTN      NumberOfDevices;
 305   UINTN      Address;
 306   PCI_TYPE01 Pci;
 307   UINT64     Attributes;
 308   UINT64     Base;
 309   UINT64     Limit;
 310   UINT64     Value;
 311   PCI_ROOT_BRIDGE_APERTURE Io, Mem, MemAbove4G, PMem, PMemAbove4G, *MemAperture;
 312   PCI_ROOT_BRIDGE *RootBridges;
 313   UINTN      BarOffsetEnd;
 314
 315
 316   *NumberOfRootBridges = 0;
 317   RootBridges = NULL;
 318
 319   //
 320   // After scanning all the PCI devices on the PCI root bridge's primary bus,
 321   // update the Primary Bus Number for the next PCI root bridge to be this PCI
 322   // root bridge's subordinate bus number + 1.
 323   //
 324   for (PrimaryBus = 0; PrimaryBus <= PCI_MAX_BUS; PrimaryBus = SubBus + 1) {
 325     SubBus = PrimaryBus;
 326     Attributes = 0;
 327     Io.Base = Mem.Base = MemAbove4G.Base = PMem.Base = PMemAbove4G.Base = MAX_UINT64;
 328     Io.Limit = Mem.Limit = MemAbove4G.Limit = PMem.Limit = PMemAbove4G.Limit = 0;
 329     //
 330     // Scan all the PCI devices on the primary bus of the PCI root bridge
 331     //
 332     for (Device = 0, NumberOfDevices = 0; Device <= PCI_MAX_DEVICE; Device++) {
 333
 334       for (Function = 0; Function <= PCI_MAX_FUNC; Function++) {
 335
 336         //
 337         // Compute the PCI configuration address of the PCI device to probe
 338         //
 339         Address = PCI_LIB_ADDRESS (PrimaryBus, Device, Function, 0);
 340
 341         //
 342         // Read the Vendor ID from the PCI Configuration Header
 343         //
 344         if (PciRead16 (Address) == MAX_UINT16) {
 345           if (Function == 0) {
 346             //
 347             // If the PCI Configuration Read fails, or a PCI device does not
 348             // exist, then skip this entire PCI device
 349             //
 350             break;
 351           } else {
 352             //
 353             // If PCI function != 0, VendorId == 0xFFFF, we continue to search
 354             // PCI function.
 355             //
 356             continue;
 357           }
 358         }
 359
 360         //
 361         // Read the entire PCI Configuration Header
 362         //
 363         PciReadBuffer (Address, sizeof (Pci), &Pci);
 364
 365         //
 366         // Increment the number of PCI device found on the primary bus of the
 367         // PCI root bridge
 368         //
 369         NumberOfDevices++;
 370
 371         //
 372         // Look for devices with the VGA Palette Snoop enabled in the COMMAND
 373         // register of the PCI Config Header
 374         //
 375         if ((Pci.Hdr.Command & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) != 0) {
 376           Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;
 377           Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
 378         }
 379
 380         BarOffsetEnd = 0;
 381
 382         //
 383         // PCI-PCI Bridge
 384         //
 385         if (IS_PCI_BRIDGE (&Pci)) {
 386           //
 387           // Get the Bus range that the PPB is decoding
 388           //
 389           if (Pci.Bridge.SubordinateBus > SubBus) {
 390             //
 391             // If the suborinate bus number of the PCI-PCI bridge is greater
 392             // than the PCI root bridge's current subordinate bus number,
 393             // then update the PCI root bridge's subordinate bus number
 394             //
 395             SubBus = Pci.Bridge.SubordinateBus;
 396           }
 397
 398           //
 399           // Get the I/O range that the PPB is decoding
 400           //
 401           Value = Pci.Bridge.IoBase & 0x0f;
 402           Base = ((UINT32) Pci.Bridge.IoBase & 0xf0) << 8;
 403           Limit = (((UINT32) Pci.Bridge.IoLimit & 0xf0) << 8) | 0x0fff;
 404           if (Value == BIT0) {
 405             Base |= ((UINT32) Pci.Bridge.IoBaseUpper16 << 16);
 406             Limit |= ((UINT32) Pci.Bridge.IoLimitUpper16 << 16);
 407           }
 408           if ((Base > 0) && (Base < Limit)) {
 409             if (Io.Base > Base) {
 410               Io.Base = Base;
 411             }
 412             if (Io.Limit < Limit) {
 413               Io.Limit = Limit;
 414             }
 415           }
 416
 417           //
 418           // Get the Memory range that the PPB is decoding
 419           //
 420           Base = ((UINT32) Pci.Bridge.MemoryBase & 0xfff0) << 16;
 421           Limit = (((UINT32) Pci.Bridge.MemoryLimit & 0xfff0) << 16) | 0xfffff;
 422           if ((Base > 0) && (Base < Limit)) {
 423             if (Mem.Base > Base) {
 424               Mem.Base = Base;
 425             }
 426             if (Mem.Limit < Limit) {
 427               Mem.Limit = Limit;
 428             }
 429           }
 430
 431           //
 432           // Get the Prefetchable Memory range that the PPB is decoding
 433           //
 434           Value = Pci.Bridge.PrefetchableMemoryBase & 0x0f;
 435           Base = ((UINT32) Pci.Bridge.PrefetchableMemoryBase & 0xfff0) << 16;
 436           Limit = (((UINT32) Pci.Bridge.PrefetchableMemoryLimit & 0xfff0)
 437                    << 16) | 0xfffff;
 438           MemAperture = &PMem;
 439           if (Value == BIT0) {
 440             Base |= LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32, 32);
 441             Limit |= LShiftU64 (Pci.Bridge.PrefetchableLimitUpper32, 32);
 442             MemAperture = &PMemAbove4G;
 443           }
 444           if ((Base > 0) && (Base < Limit)) {
 445             if (MemAperture->Base > Base) {
 446               MemAperture->Base = Base;
 447             }
 448             if (MemAperture->Limit < Limit) {
 449               MemAperture->Limit = Limit;
 450             }
 451           }
 452
 453           //
 454           // Look at the PPB Configuration for legacy decoding attributes
 455           //
 456           if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_ISA)
 457               == EFI_PCI_BRIDGE_CONTROL_ISA) {
 458             Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;
 459             Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;
 460             Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;
 461           }
 462           if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA)
 463               == EFI_PCI_BRIDGE_CONTROL_VGA) {
 464             Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;
 465             Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;
 466             Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;
 467             if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA_16)
 468                 != 0) {
 469               Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
 470               Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;
 471             }
 472           }
 473
 474           BarOffsetEnd = OFFSET_OF (PCI_TYPE01, Bridge.Bar[2]);
 475         } else {
 476           //
 477           // Parse the BARs of the PCI device to get what I/O Ranges, Memory
 478           // Ranges, and Prefetchable Memory Ranges the device is decoding
 479           //
 480           if ((Pci.Hdr.HeaderType & HEADER_LAYOUT_CODE) == HEADER_TYPE_DEVICE) {
 481             BarOffsetEnd = OFFSET_OF (PCI_TYPE00, Device.Bar[6]);
 482           }
 483         }
 484
 485         PcatPciRootBridgeParseBars (
 486           Pci.Hdr.Command,
 487           PrimaryBus,
 488           Device,
 489           Function,
 490           OFFSET_OF (PCI_TYPE00, Device.Bar),
 491           BarOffsetEnd,
 492           &Io,
 493           &Mem, &MemAbove4G,
 494           &PMem, &PMemAbove4G
 495         );
 496
 497         //
 498         // See if the PCI device is an IDE controller
 499         //
 500         if (IS_CLASS2 (&Pci, PCI_CLASS_MASS_STORAGE,
 501                        PCI_CLASS_MASS_STORAGE_IDE)) {
 502           if (Pci.Hdr.ClassCode[0] & 0x80) {
 503             Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;
 504             Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;
 505           }
 506           if (Pci.Hdr.ClassCode[0] & 0x01) {
 507             Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;
 508           }
 509           if (Pci.Hdr.ClassCode[0] & 0x04) {
 510             Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;
 511           }
 512         }
 513
 514         //
 515         // See if the PCI device is a legacy VGA controller or
 516         // a standard VGA controller
 517         //
 518         if (IS_CLASS2 (&Pci, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA) ||
 519             IS_CLASS2 (&Pci, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA)
 520            ) {
 521           Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;
 522           Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
 523           Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;
 524           Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;
 525           Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;
 526         }
 527
 528         //
 529         // See if the PCI Device is a PCI - ISA or PCI - EISA
 530         // or ISA_POSITIVIE_DECODE Bridge device
 531         //
 532         if (Pci.Hdr.ClassCode[2] == PCI_CLASS_BRIDGE) {
 533           if (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA ||
 534               Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_EISA ||
 535               Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA_PDECODE) {
 536             Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;
 537             Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;
 538             Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;
 539           }
 540         }
 541
 542         //
 543         // If this device is not a multi function device, then skip the rest
 544         // of this PCI device
 545         //
 546         if (Function == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {
 547           break;
 548         }
 549       }
 550     }
 551
 552     //
 553     // If at least one PCI device was found on the primary bus of this PCI
 554     // root bridge, then the PCI root bridge exists.
 555     //
 556     if (NumberOfDevices > 0) {
 557       RootBridges = ReallocatePool (
 558                       (*NumberOfRootBridges) * sizeof (PCI_ROOT_BRIDGE),
 559                       (*NumberOfRootBridges + 1) * sizeof (PCI_ROOT_BRIDGE),
 560                       RootBridges
 561                     );
 562       ASSERT (RootBridges != NULL);
 563
 564       AdjustRootBridgeResource (&Io, &Mem, &MemAbove4G, &PMem, &PMemAbove4G);
 565
 566       InitRootBridge (
 567         Attributes, Attributes, 0,
 568         (UINT8) PrimaryBus, (UINT8) SubBus,
 569         &Io, &Mem, &MemAbove4G, &PMem, &PMemAbove4G,
 570         &RootBridges[*NumberOfRootBridges]
 571       );
 572       RootBridges[*NumberOfRootBridges].ResourceAssigned = TRUE;
 573       //
 574       // Increment the index for the next PCI Root Bridge
 575       //
 576       (*NumberOfRootBridges)++;
 577     }
 578   }
 579
 580   return RootBridges;
 581 }