CorebootPayloadPkg/Library/PlatformBdsLib/BdsPlatform.h

   1 /** @file
   2   Head file for BDS Platform specific code
   3
   4 Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
   5 This program and the accompanying materials
   6 are licensed and made available under the terms and conditions of the BSD License
   7 which accompanies this distribution.  The full text of the license may be found at
   8 http://opensource.org/licenses/bsd-license.php
   9
  10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef _PLATFORM_SPECIFIC_BDS_PLATFORM_H_
  16 #define _PLATFORM_SPECIFIC_BDS_PLATFORM_H_
  17
  18 #include <PiDxe.h>
  19 #include <IndustryStandard/Pci.h>
  20 #include <Library/DebugLib.h>
  21 #include <Library/BaseMemoryLib.h>
  22 #include <Library/UefiBootServicesTableLib.h>
  23 #include <Library/MemoryAllocationLib.h>
  24 #include <Library/BaseLib.h>
  25 #include <Library/PcdLib.h>
  26 #include <Library/GenericBdsLib.h>
  27 #include <Library/PlatformBdsLib.h>
  28 #include <Library/UefiLib.h>
  29 #include <Library/DevicePathLib.h>
  30
  31 #include <Protocol/PciIo.h>
  32 #include <Protocol/SerialIo.h>
  33
  34 #include <Guid/GlobalVariable.h>
  35 extern BDS_CONSOLE_CONNECT_ENTRY  gPlatformConsole[];
  36 extern EFI_DEVICE_PATH_PROTOCOL   *gPlatformConnectSequence[];
  37 extern EFI_DEVICE_PATH_PROTOCOL   *gPlatformDriverOption[];
  38 extern EFI_DEVICE_PATH_PROTOCOL   *gPlatformRootBridges[];
  39 extern ACPI_HID_DEVICE_PATH       gPnp16550ComPortDeviceNode;
  40 extern UART_DEVICE_PATH           gUartDeviceNode;
  41 extern VENDOR_DEVICE_PATH         gTerminalTypeDeviceNode;
  42 extern VENDOR_DEVICE_PATH         gUartDeviceVenderNode;
  43
  44 //
  45 //
  46 //
  47 #define VarConsoleInpDev        L"ConInDev"
  48 #define VarConsoleInp           L"ConIn"
  49 #define VarConsoleOutDev        L"ConOutDev"
  50 #define VarConsoleOut           L"ConOut"
  51 #define VarErrorOutDev          L"ErrOutDev"
  52 #define VarErrorOut             L"ErrOut"
  53
  54 #define PCI_DEVICE_PATH_NODE(Func, Dev) \
  55   { \
  56     { \
  57       HARDWARE_DEVICE_PATH, \
  58       HW_PCI_DP, \
  59       { \
  60         (UINT8) (sizeof (PCI_DEVICE_PATH)), \
  61         (UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8) \
  62       } \
  63     }, \
  64     (Func), \
  65     (Dev) \
  66   }
  67
  68 #define PNPID_DEVICE_PATH_NODE(PnpId) \
  69   { \
  70     { \
  71       ACPI_DEVICE_PATH, \
  72       ACPI_DP, \
  73       { \
  74         (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), \
  75         (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) \
  76       }, \
  77     }, \
  78     EISA_PNP_ID((PnpId)), \
  79     0 \
  80   }
  81
  82 #define gPciRootBridge \
  83   PNPID_DEVICE_PATH_NODE(0x0A03)
  84 #define gPnp16550ComPort \
  85   PNPID_DEVICE_PATH_NODE(0x0501)
  86
  87 #define gUartVender \
  88   { \
  89     { \
  90       HARDWARE_DEVICE_PATH, \
  91       HW_VENDOR_DP, \
  92       { \
  93         (UINT8) (sizeof (VENDOR_DEVICE_PATH)), \
  94         (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8) \
  95       } \
  96     }, \
  97     EFI_SERIAL_IO_PROTOCOL_GUID \
  98   }
  99
 100 #define gUart \
 101   { \
 102     { \
 103       MESSAGING_DEVICE_PATH, \
 104       MSG_UART_DP, \
 105       { \
 106         (UINT8) (sizeof (UART_DEVICE_PATH)), \
 107         (UINT8) ((sizeof (UART_DEVICE_PATH)) >> 8) \
 108       } \
 109     }, \
 110     0, \
 111     115200, \
 112     8, \
 113     1, \
 114     1 \
 115   }
 116
 117 #define gPcAnsiTerminal \
 118   { \
 119     { \
 120       MESSAGING_DEVICE_PATH, \
 121       MSG_VENDOR_DP, \
 122       { \
 123         (UINT8) (sizeof (VENDOR_DEVICE_PATH)), \
 124         (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8) \
 125       } \
 126     }, \
 127     DEVICE_PATH_MESSAGING_PC_ANSI \
 128   }
 129
 130 #define gEndEntire \
 131   { \
 132     END_DEVICE_PATH_TYPE, \
 133     END_ENTIRE_DEVICE_PATH_SUBTYPE, \
 134     { \
 135       END_DEVICE_PATH_LENGTH, \
 136       0 \
 137     } \
 138   }
 139 #define PCI_CLASS_SCC          0x07
 140 #define PCI_SUBCLASS_SERIAL    0x00
 141 #define PCI_IF_16550           0x02
 142 #define IS_PCI_16550SERIAL(_p)           IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
 143
 144 #define IS_PCI_ISA_PDECODE(_p)        IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA_PDECODE, 0)
 145
 146 //
 147 // Platform Root Bridge
 148 //
 149 typedef struct {
 150   ACPI_HID_DEVICE_PATH      PciRootBridge;
 151   EFI_DEVICE_PATH_PROTOCOL  End;
 152 } PLATFORM_ROOT_BRIDGE_DEVICE_PATH;
 153 EFI_STATUS
 154 PlatformBdsNoConsoleAction (
 155   VOID
 156   );
 157 VOID
 158 PlatformBdsEnterFrontPage (
 159   IN UINT16                 TimeoutDefault,
 160   IN BOOLEAN                ConnectAllHappened
 161   );
 162 #endif // _PLATFORM_SPECIFIC_BDS_PLATFORM_H_