2 Head file for BDS Platform specific code
4 Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #ifndef _PLATFORM_SPECIFIC_BDS_PLATFORM_H_
16 #define _PLATFORM_SPECIFIC_BDS_PLATFORM_H_
19 #include <IndustryStandard/Pci.h>
20 #include <Library/DebugLib.h>
21 #include <Library/BaseMemoryLib.h>
22 #include <Library/UefiBootServicesTableLib.h>
23 #include <Library/MemoryAllocationLib.h>
24 #include <Library/BaseLib.h>
25 #include <Library/PcdLib.h>
26 #include <Library/GenericBdsLib.h>
27 #include <Library/PlatformBdsLib.h>
28 #include <Library/UefiLib.h>
29 #include <Library/DevicePathLib.h>
31 #include <Protocol/PciIo.h>
33 #include <Guid/GlobalVariable.h>
34 extern BDS_CONSOLE_CONNECT_ENTRY gPlatformConsole
[];
35 extern EFI_DEVICE_PATH_PROTOCOL
*gPlatformConnectSequence
[];
36 extern EFI_DEVICE_PATH_PROTOCOL
*gPlatformDriverOption
[];
37 extern EFI_DEVICE_PATH_PROTOCOL
*gPlatformRootBridges
[];
38 extern ACPI_HID_DEVICE_PATH gPnp16550ComPortDeviceNode
;
39 extern UART_DEVICE_PATH gUartDeviceNode
;
40 extern VENDOR_DEVICE_PATH gTerminalTypeDeviceNode
;
41 extern VENDOR_DEVICE_PATH gUartDeviceVendorNode
;
46 #define VarConsoleInpDev L"ConInDev"
47 #define VarConsoleInp L"ConIn"
48 #define VarConsoleOutDev L"ConOutDev"
49 #define VarConsoleOut L"ConOut"
50 #define VarErrorOutDev L"ErrOutDev"
51 #define VarErrorOut L"ErrOut"
53 #define PCI_DEVICE_PATH_NODE(Func, Dev) \
56 HARDWARE_DEVICE_PATH, \
59 (UINT8) (sizeof (PCI_DEVICE_PATH)), \
60 (UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8) \
67 #define PNPID_DEVICE_PATH_NODE(PnpId) \
73 (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), \
74 (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) \
77 EISA_PNP_ID((PnpId)), \
81 #define gPciRootBridge \
82 PNPID_DEVICE_PATH_NODE(0x0A03)
83 #define gPnp16550ComPort \
84 PNPID_DEVICE_PATH_NODE(0x0501)
89 HARDWARE_DEVICE_PATH, \
92 (UINT8) (sizeof (VENDOR_DEVICE_PATH)), \
93 (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8) \
96 {0xD3987D4B, 0x971A, 0x435F, {0x8C, 0xAF, 0x49, 0x67, 0xEB, 0x62, 0x72, 0x41}} \
102 MESSAGING_DEVICE_PATH, \
105 (UINT8) (sizeof (UART_DEVICE_PATH)), \
106 (UINT8) ((sizeof (UART_DEVICE_PATH)) >> 8) \
116 #define gPcAnsiTerminal \
119 MESSAGING_DEVICE_PATH, \
122 (UINT8) (sizeof (VENDOR_DEVICE_PATH)), \
123 (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8) \
126 DEVICE_PATH_MESSAGING_PC_ANSI \
131 END_DEVICE_PATH_TYPE, \
132 END_ENTIRE_DEVICE_PATH_SUBTYPE, \
134 END_DEVICE_PATH_LENGTH, \
138 #define PCI_CLASS_SCC 0x07
139 #define PCI_SUBCLASS_SERIAL 0x00
140 #define PCI_IF_16550 0x02
141 #define IS_PCI_16550SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
143 #define IS_PCI_ISA_PDECODE(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA_PDECODE, 0)
146 // Platform Root Bridge
149 ACPI_HID_DEVICE_PATH PciRootBridge
;
150 EFI_DEVICE_PATH_PROTOCOL End
;
151 } PLATFORM_ROOT_BRIDGE_DEVICE_PATH
;
153 PlatformBdsNoConsoleAction (
157 PlatformBdsEnterFrontPage (
158 IN UINT16 TimeoutDefault
,
159 IN BOOLEAN ConnectAllHappened
161 #endif // _PLATFORM_SPECIFIC_BDS_PLATFORM_H_