DuetPkg/Include/CpuIA32.h

   1 /*++
   2
   3 Copyright (c) 2006, Intel Corporation. All rights reserved.
   4 This software and associated documentation (if any) is furnished
   5 under a license and may only be used or copied in accordance
   6 with the terms of the license. Except as permitted by such
   7 license, no part of this software or documentation may be
   8 reproduced, stored in a retrieval system, or transmitted in any
   9 form or by any means without the express written consent of
  10 Intel Corporation.
  11
  12 Module Name:
  13
  14   CpuIA32.h
  15
  16 Abstract:
  17
  18   Basic Definition for IA32 Architecture.
  19
  20 --*/
  21
  22 #ifndef _CPU_IA32_H_
  23 #define _CPU_IA32_H_
  24
  25 typedef struct {
  26   UINT32  RegEax;
  27   UINT32  RegEbx;
  28   UINT32  RegEcx;
  29   UINT32  RegEdx;
  30 } EFI_CPUID_REGISTER;
  31
  32 #pragma pack(1)
  33 //
  34 // Definition for IA32 microcode format
  35 //
  36 typedef struct {
  37   UINT32  HeaderVersion;
  38   UINT32  UpdateRevision;
  39   UINT32  Date;
  40   UINT32  ProcessorId;
  41   UINT32  Checksum;
  42   UINT32  LoaderRevision;
  43   UINT32  ProcessorFlags;
  44   UINT32  DataSize;
  45   UINT32  TotalSize;
  46   UINT8   Reserved[12];
  47 } EFI_CPU_MICROCODE_HEADER;
  48
  49 typedef struct {
  50   UINT32  ExtendedSignatureCount;
  51   UINT32  ExtendedTableChecksum;
  52   UINT8   Reserved[12];
  53 } EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER;
  54
  55 typedef struct {
  56   UINT32  ProcessorSignature;
  57   UINT32  ProcessorFlag;
  58   UINT32  ProcessorChecksum;
  59 } EFI_CPU_MICROCODE_EXTENDED_TABLE;
  60
  61 //
  62 // The MS compiler doesn't handle QWORDs very well.  So break
  63 // them into DWORDs to circumvent the problem.
  64 //
  65 typedef union _MSR_REGISTER {
  66   UINT64  Qword;
  67
  68   struct _DWORDS {
  69     UINT32  Low;
  70     UINT32  High;
  71   } Dwords;
  72
  73   struct _BYTES {
  74     UINT8 FirstByte;
  75     UINT8 SecondByte;
  76     UINT8 ThirdByte;
  77     UINT8 FouthByte;
  78     UINT8 FifthByte;
  79     UINT8 SixthByte;
  80     UINT8 SeventhByte;
  81     UINT8 EighthByte;
  82   } Bytes;
  83
  84 } MSR_REGISTER;
  85
  86 #pragma pack()
  87
  88 //
  89 // Definition for CPUID Index
  90 //
  91 #define EFI_CPUID_SIGNATURE                   0x0
  92 #define EFI_CPUID_VERSION_INFO                0x1
  93 #define EFI_CPUID_CACHE_INFO                  0x2
  94 #define EFI_CPUID_SERIAL_NUMBER               0x3
  95 #define EFI_CPUID_EXTENDED_FUNCTION           0x80000000
  96 #define EFI_CPUID_EXTENDED_CPU_SIG            0x80000001
  97 #define EFI_CPUID_BRAND_STRING1               0x80000002
  98 #define EFI_CPUID_BRAND_STRING2               0x80000003
  99 #define EFI_CPUID_BRAND_STRING3               0x80000004
 100 #define EFI_CPUID_ADDRESS_SIZE                0x80000008
 101
 102 //
 103 // Definition for MSR address
 104 //
 105 #define EFI_MSR_IA32_PLATFORM_ID              0x17
 106 #define EFI_MSR_IA32_APIC_BASE                0x1B
 107 #define EFI_MSR_EBC_HARD_POWERON              0x2A
 108 #define EFI_MSR_EBC_SOFT_POWERON              0x2B
 109 #define EFI_MSR_EBC_FREQUENCY_ID              0x2C
 110 #define MSR_IA32_FEATURE_CONTROL              0x3A
 111 #define EFI_MSR_IA32_BIOS_UPDT_TRIG           0x79
 112 #define EFI_MSR_IA32_BIOS_SIGN_ID             0x8B
 113 #define EFI_MSR_PSB_CLOCK_STATUS              0xCD
 114 #define MSR_EXT_CONFIG                        0xEE
 115 #define EFI_IA32_MCG_CAP                      0x179
 116 #define EFI_IA32_MCG_CTL                      0x17B
 117
 118 #define EFI_MSR_IA32_PERF_STS                 0x198
 119 #define EFI_MSR_IA32_PERF_CTL                 0x199
 120 #define EFI_MSR_IA32_CLOCK_MODULATION         0x19A
 121 #define MSR_IA32_THERMAL_INTERRUPT            0x19B
 122 #define EFI_MSR_IA32_THERM_STATUS             0x19C
 123 #define EFI_MSR_GV_THERM                      0x19D
 124 #define MSR_IA32_MISC_ENABLE                  0x1A0
 125 #define MSR_PIC_SENS_CFG                      0x1AA
 126
 127 #define EFI_IA32_MC0_CTL                      0x400
 128 #define EFI_IA32_MC0_STATUS                   0x401
 129 #define MSR_PECI_CONTROL                      0x5A0
 130
 131 //
 132 // Definition for MTRR address and related values
 133 //
 134 #define EFI_IA32_MTRR_FIX64K_00000            0x250
 135 #define EFI_IA32_MTRR_FIX16K_80000            0x258
 136 #define EFI_IA32_MTRR_FIX16K_A0000            0x259
 137 #define EFI_IA32_MTRR_FIX4K_C0000             0x268
 138 #define EFI_IA32_MTRR_FIX4K_C8000             0x269
 139 #define EFI_IA32_MTRR_FIX4K_D0000             0x26A
 140 #define EFI_IA32_MTRR_FIX4K_D8000             0x26B
 141 #define EFI_IA32_MTRR_FIX4K_E0000             0x26C
 142 #define EFI_IA32_MTRR_FIX4K_E8000             0x26D
 143 #define EFI_IA32_MTRR_FIX4K_F0000             0x26E
 144 #define EFI_IA32_MTRR_FIX4K_F8000             0x26F
 145 #define EFI_CACHE_VARIABLE_MTRR_BASE          0x200
 146 #define EFI_CACHE_VARIABLE_MTRR_END           0x20F
 147 #define EFI_CACHE_IA32_MTRR_DEF_TYPE          0x2FF
 148
 149 #define EFI_CACHE_VALID_ADDRESS               0xFFFFFF000
 150 #define EFI_MSR_VALID_MASK                    0xFFFFFFFFF
 151 #define EFI_CACHE_MTRR_VALID                  0x800
 152 #define EFI_CACHE_FIXED_MTRR_VALID            0x400
 153
 154 #define EFI_CACHE_UNCACHEABLE                 0
 155 #define EFI_CACHE_WRITECOMBINING              1
 156 #define EFI_CACHE_WRITETHROUGH                4
 157 #define EFI_CACHE_WRITEPROTECTED              5
 158 #define EFI_CACHE_WRITEBACK                   6
 159
 160 //
 161 // Definition for Local APIC registers and related values
 162 //
 163 #define LOCAL_APIC_LVT_TIMER                  0x320
 164 #define LOCAL_APIC_TIMER_INIT_COUNT           0x380
 165 #define LOCAL_APIC_TIMER_COUNT                0x390
 166 #define LOCAL_APIC_TIMER_DIVIDE               0x3E0
 167
 168
 169 #define DELIVERY_MODE_FIXED                   0x0
 170 #define DELIVERY_MODE_LOWEST_PRIORITY         0x1
 171 #define DELIVERY_MODE_SMI                     0x2
 172 #define DELIVERY_MODE_REMOTE_READ             0x3
 173 #define DELIVERY_MODE_NMI                     0x4
 174 #define DELIVERY_MODE_INIT                    0x5
 175 #define DELIVERY_MODE_SIPI                    0x6
 176
 177 #define TRIGGER_MODE_EDGE                     0x0
 178 #define TRIGGER_MODE_LEVEL                    0x1
 179
 180 //
 181 // CPU System Memory Map Definition
 182 //
 183 #define CPU_MSI_MEMORY_BASE                   0xFEE00000
 184 #define CPU_MSI_MEMORY_SIZE                   0x100000
 185
 186
 187 #endif