DuetPkg/Include/CpuIA32.h

   1 /** @file
   2   Basic Definition for IA32 Architecture.
   3
   4 Copyright (c) 2006 - 2009, Intel Corporation
   5 All rights reserved. This program and the accompanying materials
   6 are licensed and made available under the terms and conditions of the BSD License
   7 which accompanies this distribution.  The full text of the license may be found at
   8 http://opensource.org/licenses/bsd-license.php
   9
  10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef _CPU_IA32_H_
  16 #define _CPU_IA32_H_
  17
  18 typedef struct {
  19   UINT32  RegEax;
  20   UINT32  RegEbx;
  21   UINT32  RegEcx;
  22   UINT32  RegEdx;
  23 } EFI_CPUID_REGISTER;
  24
  25 #pragma pack(1)
  26 //
  27 // Definition for IA32 microcode format
  28 //
  29 typedef struct {
  30   UINT32  HeaderVersion;
  31   UINT32  UpdateRevision;
  32   UINT32  Date;
  33   UINT32  ProcessorId;
  34   UINT32  Checksum;
  35   UINT32  LoaderRevision;
  36   UINT32  ProcessorFlags;
  37   UINT32  DataSize;
  38   UINT32  TotalSize;
  39   UINT8   Reserved[12];
  40 } EFI_CPU_MICROCODE_HEADER;
  41
  42 typedef struct {
  43   UINT32  ExtendedSignatureCount;
  44   UINT32  ExtendedTableChecksum;
  45   UINT8   Reserved[12];
  46 } EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER;
  47
  48 typedef struct {
  49   UINT32  ProcessorSignature;
  50   UINT32  ProcessorFlag;
  51   UINT32  ProcessorChecksum;
  52 } EFI_CPU_MICROCODE_EXTENDED_TABLE;
  53
  54 //
  55 // The MS compiler doesn't handle QWORDs very well.  So break
  56 // them into DWORDs to circumvent the problem.
  57 //
  58 typedef union _MSR_REGISTER {
  59   UINT64  Qword;
  60
  61   struct _DWORDS {
  62     UINT32  Low;
  63     UINT32  High;
  64   } Dwords;
  65
  66   struct _BYTES {
  67     UINT8 FirstByte;
  68     UINT8 SecondByte;
  69     UINT8 ThirdByte;
  70     UINT8 FouthByte;
  71     UINT8 FifthByte;
  72     UINT8 SixthByte;
  73     UINT8 SeventhByte;
  74     UINT8 EighthByte;
  75   } Bytes;
  76
  77 } MSR_REGISTER;
  78
  79 #pragma pack()
  80
  81 //
  82 // Definition for CPUID Index
  83 //
  84 #define EFI_CPUID_SIGNATURE                   0x0
  85 #define EFI_CPUID_VERSION_INFO                0x1
  86 #define EFI_CPUID_CACHE_INFO                  0x2
  87 #define EFI_CPUID_SERIAL_NUMBER               0x3
  88 #define EFI_CPUID_EXTENDED_FUNCTION           0x80000000
  89 #define EFI_CPUID_EXTENDED_CPU_SIG            0x80000001
  90 #define EFI_CPUID_BRAND_STRING1               0x80000002
  91 #define EFI_CPUID_BRAND_STRING2               0x80000003
  92 #define EFI_CPUID_BRAND_STRING3               0x80000004
  93 #define EFI_CPUID_ADDRESS_SIZE                0x80000008
  94
  95 //
  96 // Definition for MSR address
  97 //
  98 #define EFI_MSR_IA32_PLATFORM_ID              0x17
  99 #define EFI_MSR_IA32_APIC_BASE                0x1B
 100 #define EFI_MSR_EBC_HARD_POWERON              0x2A
 101 #define EFI_MSR_EBC_SOFT_POWERON              0x2B
 102 #define EFI_MSR_EBC_FREQUENCY_ID              0x2C
 103 #define MSR_IA32_FEATURE_CONTROL              0x3A
 104 #define EFI_MSR_IA32_BIOS_UPDT_TRIG           0x79
 105 #define EFI_MSR_IA32_BIOS_SIGN_ID             0x8B
 106 #define EFI_MSR_PSB_CLOCK_STATUS              0xCD
 107 #define MSR_EXT_CONFIG                        0xEE
 108 #define EFI_IA32_MCG_CAP                      0x179
 109 #define EFI_IA32_MCG_CTL                      0x17B
 110
 111 #define EFI_MSR_IA32_PERF_STS                 0x198
 112 #define EFI_MSR_IA32_PERF_CTL                 0x199
 113 #define EFI_MSR_IA32_CLOCK_MODULATION         0x19A
 114 #define MSR_IA32_THERMAL_INTERRUPT            0x19B
 115 #define EFI_MSR_IA32_THERM_STATUS             0x19C
 116 #define EFI_MSR_GV_THERM                      0x19D
 117 #define MSR_IA32_MISC_ENABLE                  0x1A0
 118 #define MSR_PIC_SENS_CFG                      0x1AA
 119
 120 #define EFI_IA32_MC0_CTL                      0x400
 121 #define EFI_IA32_MC0_STATUS                   0x401
 122 #define MSR_PECI_CONTROL                      0x5A0
 123
 124 //
 125 // Definition for MTRR address and related values
 126 //
 127 #define EFI_IA32_MTRR_FIX64K_00000            0x250
 128 #define EFI_IA32_MTRR_FIX16K_80000            0x258
 129 #define EFI_IA32_MTRR_FIX16K_A0000            0x259
 130 #define EFI_IA32_MTRR_FIX4K_C0000             0x268
 131 #define EFI_IA32_MTRR_FIX4K_C8000             0x269
 132 #define EFI_IA32_MTRR_FIX4K_D0000             0x26A
 133 #define EFI_IA32_MTRR_FIX4K_D8000             0x26B
 134 #define EFI_IA32_MTRR_FIX4K_E0000             0x26C
 135 #define EFI_IA32_MTRR_FIX4K_E8000             0x26D
 136 #define EFI_IA32_MTRR_FIX4K_F0000             0x26E
 137 #define EFI_IA32_MTRR_FIX4K_F8000             0x26F
 138 #define EFI_CACHE_VARIABLE_MTRR_BASE          0x200
 139 #define EFI_CACHE_VARIABLE_MTRR_END           0x20F
 140 #define EFI_CACHE_IA32_MTRR_DEF_TYPE          0x2FF
 141
 142 #define EFI_CACHE_VALID_ADDRESS               0xFFFFFF000
 143 #define EFI_MSR_VALID_MASK                    0xFFFFFFFFF
 144 #define EFI_CACHE_MTRR_VALID                  0x800
 145 #define EFI_CACHE_FIXED_MTRR_VALID            0x400
 146
 147 #define EFI_CACHE_UNCACHEABLE                 0
 148 #define EFI_CACHE_WRITECOMBINING              1
 149 #define EFI_CACHE_WRITETHROUGH                4
 150 #define EFI_CACHE_WRITEPROTECTED              5
 151 #define EFI_CACHE_WRITEBACK                   6
 152
 153 //
 154 // Definition for Local APIC registers and related values
 155 //
 156 #define LOCAL_APIC_LVT_TIMER                  0x320
 157 #define LOCAL_APIC_TIMER_INIT_COUNT           0x380
 158 #define LOCAL_APIC_TIMER_COUNT                0x390
 159 #define LOCAL_APIC_TIMER_DIVIDE               0x3E0
 160
 161
 162 #define DELIVERY_MODE_FIXED                   0x0
 163 #define DELIVERY_MODE_LOWEST_PRIORITY         0x1
 164 #define DELIVERY_MODE_SMI                     0x2
 165 #define DELIVERY_MODE_REMOTE_READ             0x3
 166 #define DELIVERY_MODE_NMI                     0x4
 167 #define DELIVERY_MODE_INIT                    0x5
 168 #define DELIVERY_MODE_SIPI                    0x6
 169
 170 #define TRIGGER_MODE_EDGE                     0x0
 171 #define TRIGGER_MODE_LEVEL                    0x1
 172
 173 //
 174 // CPU System Memory Map Definition
 175 //
 176 #define CPU_MSI_MEMORY_BASE                   0xFEE00000
 177 #define CPU_MSI_MEMORY_SIZE                   0x100000
 178
 179
 180 #endif