3 Copyright (c) 2017 - 2019, ARM Limited. All rights reserved.
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14 - Cm or CM - Configuration Manager
16 - Std or STD - Standard
19 #ifndef ARM_NAMESPACE_OBJECTS_H_
20 #define ARM_NAMESPACE_OBJECTS_H_
22 #include <StandardNameSpaceObjects.h>
26 /** The EARM_OBJECT_ID enum describes the Object IDs
29 typedef enum ArmObjectID
{
30 EArmObjReserved
, ///< 0 - Reserved
31 EArmObjBootArchInfo
, ///< 1 - Boot Architecture Info
32 EArmObjCpuInfo
, ///< 2 - CPU Info
33 EArmObjPowerManagementProfileInfo
, ///< 3 - Power Management Profile Info
34 EArmObjGicCInfo
, ///< 4 - GIC CPU Interface Info
35 EArmObjGicDInfo
, ///< 5 - GIC Distributor Info
36 EArmObjGicMsiFrameInfo
, ///< 6 - GIC MSI Frame Info
37 EArmObjGicRedistributorInfo
, ///< 7 - GIC Redistributor Info
38 EArmObjGicItsInfo
, ///< 8 - GIC ITS Info
39 EArmObjSerialConsolePortInfo
, ///< 9 - Serial Console Port Info
40 EArmObjSerialDebugPortInfo
, ///< 10 - Serial Debug Port Info
41 EArmObjGenericTimerInfo
, ///< 11 - Generic Timer Info
42 EArmObjPlatformGTBlockInfo
, ///< 12 - Platform GT Block Info
43 EArmObjGTBlockTimerFrameInfo
, ///< 13 - Generic Timer Block Frame Info
44 EArmObjPlatformGenericWatchdogInfo
, ///< 14 - Platform Generic Watchdog
45 EArmObjPciConfigSpaceInfo
, ///< 15 - PCI Configuration Space Info
46 EArmObjHypervisorVendorIdentity
, ///< 16 - Hypervisor Vendor Id
47 EArmObjFixedFeatureFlags
, ///< 17 - Fixed feature flags for FADT
48 EArmObjItsGroup
, ///< 18 - ITS Group
49 EArmObjNamedComponent
, ///< 19 - Named Component
50 EArmObjRootComplex
, ///< 20 - Root Complex
51 EArmObjSmmuV1SmmuV2
, ///< 21 - SMMUv1 or SMMUv2
52 EArmObjSmmuV3
, ///< 22 - SMMUv3
53 EArmObjPmcg
, ///< 23 - PMCG
54 EArmObjGicItsIdentifierArray
, ///< 24 - GIC ITS Identifier Array
55 EArmObjIdMappingArray
, ///< 25 - ID Mapping Array
56 EArmObjSmmuInterruptArray
, ///< 26 - SMMU Interrupt Array
60 /** A structure that describes the
61 ARM Boot Architecture flags.
63 typedef struct CmArmBootArchInfo
{
64 /** This is the ARM_BOOT_ARCH flags field of the FADT Table
65 described in the ACPI Table Specification.
68 } CM_ARM_BOOT_ARCH_INFO
;
70 typedef struct CmArmCpuInfo
{
71 // Reserved for use when SMBIOS tables are implemented
74 typedef struct CmArmCpuInfoList
{
76 CM_ARM_CPU_INFO
* CpuInfo
;
77 } CM_ARM_CPU_INFO_LIST
;
79 /** A structure that describes the
80 Power Management Profile Information for the Platform.
82 typedef struct CmArmPowerManagementProfileInfo
{
83 /** This is the Preferred_PM_Profile field of the FADT Table
84 described in the ACPI Specification
86 UINT8 PowerManagementProfile
;
87 } CM_ARM_POWER_MANAGEMENT_PROFILE_INFO
;
89 /** A structure that describes the
90 GIC CPU Interface for the Platform.
92 typedef struct CmArmGicCInfo
{
93 /// The GIC CPU Interface number.
94 UINT32 CPUInterfaceNumber
;
96 /** The ACPI Processor UID. This must match the
97 _UID of the CPU Device object information described
98 in the DSDT/SSDT for the CPU.
100 UINT32 AcpiProcessorUid
;
102 /** The flags field as described by the GICC structure
103 in the ACPI Specification.
107 /** The parking protocol version field as described by
108 the GICC structure in the ACPI Specification.
110 UINT32 ParkingProtocolVersion
;
112 /** The Performance Interrupt field as described by
113 the GICC structure in the ACPI Specification.
115 UINT32 PerformanceInterruptGsiv
;
117 /** The CPU Parked address field as described by
118 the GICC structure in the ACPI Specification.
120 UINT64 ParkedAddress
;
122 /** The base address for the GIC CPU Interface
123 as described by the GICC structure in the
126 UINT64 PhysicalBaseAddress
;
128 /** The base address for GICV interface
129 as described by the GICC structure in the
134 /** The base address for GICH interface
135 as described by the GICC structure in the
140 /** The GICV maintenance interrupt
141 as described by the GICC structure in the
144 UINT32 VGICMaintenanceInterrupt
;
146 /** The base address for GICR interface
147 as described by the GICC structure in the
150 UINT64 GICRBaseAddress
;
152 /** The MPIDR for the CPU
153 as described by the GICC structure in the
158 /** The Processor Power Efficiency class
159 as described by the GICC structure in the
162 UINT8 ProcessorPowerEfficiencyClass
;
165 /** A structure that describes the
166 GIC Distributor information for the Platform.
168 typedef struct CmArmGicDInfo
{
169 /// The Physical Base address for the GIC Distributor.
170 UINT64 PhysicalBaseAddress
;
172 /** The global system interrupt
173 number where this GIC Distributor's
174 interrupt inputs start.
176 UINT32 SystemVectorBase
;
178 /** The GIC version as described
179 by the GICD structure in the
185 /** A structure that describes the
186 GIC MSI Frame information for the Platform.
188 typedef struct CmArmGicMsiFrameInfo
{
189 /// The GIC MSI Frame ID
190 UINT32 GicMsiFrameId
;
192 /// The Physical base address for the MSI Frame
193 UINT64 PhysicalBaseAddress
;
195 /** The GIC MSI Frame flags
196 as described by the GIC MSI frame
197 structure in the ACPI Specification.
201 /// SPI Count used by this frame
204 /// SPI Base used by this frame
206 } CM_ARM_GIC_MSI_FRAME_INFO
;
208 /** A structure that describes the
209 GIC Redistributor information for the Platform.
211 typedef struct CmArmGicRedistInfo
{
212 /** The physical address of a page range
213 containing all GIC Redistributors.
215 UINT64 DiscoveryRangeBaseAddress
;
217 /// Length of the GIC Redistributor Discovery page range
218 UINT32 DiscoveryRangeLength
;
219 } CM_ARM_GIC_REDIST_INFO
;
221 /** A structure that describes the
222 GIC Interrupt Translation Service information for the Platform.
224 typedef struct CmArmGicItsInfo
{
228 /// The physical address for the Interrupt Translation Service
229 UINT64 PhysicalBaseAddress
;
230 } CM_ARM_GIC_ITS_INFO
;
232 /** A structure that describes the
233 Serial Port information for the Platform.
235 typedef struct CmArmSerialPortInfo
{
236 /// The physical base address for the serial port
239 /// The serial port interrupt
242 /// The serial port baud rate
245 /// The serial port clock
248 /// Serial Port subtype
250 } CM_ARM_SERIAL_PORT_INFO
;
252 /** A structure that describes the
253 Generic Timer information for the Platform.
255 typedef struct CmArmGenericTimerInfo
{
256 /// The physical base address for the counter control frame
257 UINT64 CounterControlBaseAddress
;
259 /// The physical base address for the counter read frame
260 UINT64 CounterReadBaseAddress
;
262 /// The secure PL1 timer interrupt
263 UINT32 SecurePL1TimerGSIV
;
265 /// The secure PL1 timer flags
266 UINT32 SecurePL1TimerFlags
;
268 /// The non-secure PL1 timer interrupt
269 UINT32 NonSecurePL1TimerGSIV
;
271 /// The non-secure PL1 timer flags
272 UINT32 NonSecurePL1TimerFlags
;
274 /// The virtual timer interrupt
275 UINT32 VirtualTimerGSIV
;
277 /// The virtual timer flags
278 UINT32 VirtualTimerFlags
;
280 /// The non-secure PL2 timer interrupt
281 UINT32 NonSecurePL2TimerGSIV
;
283 /// The non-secure PL2 timer flags
284 UINT32 NonSecurePL2TimerFlags
;
285 } CM_ARM_GENERIC_TIMER_INFO
;
287 /** A structure that describes the
288 Platform Generic Block Timer Frame information for the Platform.
290 typedef struct CmArmGTBlockTimerFrameInfo
{
291 /// The Generic Timer frame number
294 /// The physical base address for the CntBase block
295 UINT64 PhysicalAddressCntBase
;
297 /// The physical base address for the CntEL0Base block
298 UINT64 PhysicalAddressCntEL0Base
;
300 /// The physical timer interrupt
301 UINT32 PhysicalTimerGSIV
;
303 /** The physical timer flags as described by the GT Block
304 Timer frame Structure in the ACPI Specification.
306 UINT32 PhysicalTimerFlags
;
308 /// The virtual timer interrupt
309 UINT32 VirtualTimerGSIV
;
311 /** The virtual timer flags as described by the GT Block
312 Timer frame Structure in the ACPI Specification.
314 UINT32 VirtualTimerFlags
;
316 /** The common timer flags as described by the GT Block
317 Timer frame Structure in the ACPI Specification.
320 } CM_ARM_GTBLOCK_TIMER_FRAME_INFO
;
322 /** A structure that describes the
323 Platform Generic Block Timer information for the Platform.
325 typedef struct CmArmGTBlockInfo
{
326 /// The physical base address for the GT Block Timer structure
327 UINT64 GTBlockPhysicalAddress
;
329 /// The number of timer frames implemented in the GT Block
330 UINT32 GTBlockTimerFrameCount
;
332 /// Reference token for the GT Block timer frame list
333 CM_OBJECT_TOKEN GTBlockTimerFrameToken
;
334 } CM_ARM_GTBLOCK_INFO
;
336 /** A structure that describes the
337 SBSA Generic Watchdog information for the Platform.
339 typedef struct CmArmGenericWatchdogInfo
{
340 /// The physical base address of the SBSA Watchdog control frame
341 UINT64 ControlFrameAddress
;
343 /// The physical base address of the SBSA Watchdog refresh frame
344 UINT64 RefreshFrameAddress
;
346 /// The watchdog interrupt
349 /** The flags for the watchdog as described by the SBSA watchdog
350 structure in the ACPI specification.
353 } CM_ARM_GENERIC_WATCHDOG_INFO
;
355 /** A structure that describes the
356 PCI Configuration Space information for the Platform.
358 typedef struct CmArmPciConfigSpaceInfo
{
359 /// The physical base address for the PCI segment
362 /// The PCI segment group number
363 UINT16 PciSegmentGroupNumber
;
365 /// The start bus number
366 UINT8 StartBusNumber
;
368 /// The end bus number
370 } CM_ARM_PCI_CONFIG_SPACE_INFO
;
372 /** A structure that describes the
373 Hypervisor Vendor ID information for the Platform.
375 typedef struct CmArmHypervisorVendorId
{
376 /// The hypervisor Vendor ID
377 UINT64 HypervisorVendorId
;
378 } CM_ARM_HYPERVISOR_VENDOR_ID
;
380 /** A structure that describes the
381 Fixed feature flags for the Platform.
383 typedef struct CmArmFixedFeatureFlags
{
384 /// The Fixed feature flags
386 } CM_ARM_FIXED_FEATURE_FLAGS
;
388 /** A structure that describes the
389 ITS Group node for the Platform.
391 typedef struct CmArmItsGroupNode
{
392 /// An unique token used to ideintify this object
393 CM_OBJECT_TOKEN Token
;
394 /// The number of ITS identifiers in the ITS node
396 /// Reference token for the ITS identifier array
397 CM_OBJECT_TOKEN ItsIdToken
;
398 } CM_ARM_ITS_GROUP_NODE
;
400 /** A structure that describes the
401 GIC ITS Identifiers for an ITS Group node.
403 typedef struct CmArmGicItsIdentifier
{
404 /// The ITS Identifier
406 } CM_ARM_ITS_IDENTIFIER
;
408 /** A structure that describes the
409 Named component node for the Platform.
411 typedef struct CmArmNamedComponentNode
{
412 /// An unique token used to ideintify this object
413 CM_OBJECT_TOKEN Token
;
414 /// Number of ID mappings
415 UINT32 IdMappingCount
;
416 /// Reference token for the ID mapping array
417 CM_OBJECT_TOKEN IdMappingToken
;
419 /// Flags for the named component
422 /// Memory access properties : Cache coherent attributes
423 UINT32 CacheCoherent
;
424 /// Memory access properties : Allocation hints
425 UINT8 AllocationHints
;
426 /// Memory access properties : Memory access flags
427 UINT8 MemoryAccessFlags
;
429 /// Memory access properties : Address size limit
430 UINT8 AddressSizeLimit
;
431 /** ASCII Null terminated string with the full path to
432 the entry in the namespace for this object.
435 } CM_ARM_NAMED_COMPONENT_NODE
;
437 /** A structure that describes the
438 Root complex node for the Platform.
440 typedef struct CmArmRootComplexNode
{
441 /// An unique token used to ideintify this object
442 CM_OBJECT_TOKEN Token
;
443 /// Number of ID mappings
444 UINT32 IdMappingCount
;
445 /// Reference token for the ID mapping array
446 CM_OBJECT_TOKEN IdMappingToken
;
448 /// Memory access properties : Cache coherent attributes
449 UINT32 CacheCoherent
;
450 /// Memory access properties : Allocation hints
451 UINT8 AllocationHints
;
452 /// Memory access properties : Memory access flags
453 UINT8 MemoryAccessFlags
;
457 /// PCI segment number
458 UINT32 PciSegmentNumber
;
459 /// Memory address size limit
460 UINT8 MemoryAddressSize
;
461 } CM_ARM_ROOT_COMPLEX_NODE
;
463 /** A structure that describes the
464 SMMUv1 or SMMUv2 node for the Platform.
466 typedef struct CmArmSmmuV1SmmuV2Node
{
467 /// An unique token used to ideintify this object
468 CM_OBJECT_TOKEN Token
;
469 /// Number of ID mappings
470 UINT32 IdMappingCount
;
471 /// Reference token for the ID mapping array
472 CM_OBJECT_TOKEN IdMappingToken
;
474 /// SMMU Base Address
476 /// Length of the memory range covered by the SMMU
483 /// Number of context interrupts
484 UINT32 ContextInterruptCount
;
485 /// Reference token for the context interrupt array
486 CM_OBJECT_TOKEN ContextInterruptToken
;
488 /// Number of PMU interrupts
489 UINT32 PmuInterruptCount
;
490 /// Reference token for the PMU interrupt array
491 CM_OBJECT_TOKEN PmuInterruptToken
;
493 /// GSIV of the SMMU_NSgIrpt interrupt
495 /// SMMU_NSgIrpt interrupt flags
496 UINT32 SMMU_NSgIrptFlags
;
497 /// GSIV of the SMMU_NSgCfgIrpt interrupt
498 UINT32 SMMU_NSgCfgIrpt
;
499 /// SMMU_NSgCfgIrpt interrupt flags
500 UINT32 SMMU_NSgCfgIrptFlags
;
501 } CM_ARM_SMMUV1_SMMUV2_NODE
;
503 /** A structure that describes the
504 SMMUv3 node for the Platform.
506 typedef struct CmArmSmmuV3Node
{
507 /// An unique token used to ideintify this object
508 CM_OBJECT_TOKEN Token
;
509 /// Number of ID mappings
510 UINT32 IdMappingCount
;
511 /// Reference token for the ID mapping array
512 CM_OBJECT_TOKEN IdMappingToken
;
514 /// SMMU Base Address
522 /// GSIV of the Event interrupt if SPI based
523 UINT32 EventInterrupt
;
524 /// PRI Interrupt if SPI based
526 /// GERR interrupt if GSIV based
527 UINT32 GerrInterrupt
;
528 /// Sync interrupt if GSIV based
529 UINT32 SyncInterrupt
;
531 /// Proximity domain flag
532 UINT32 ProximityDomain
;
533 /// Index into the array of ID mapping
534 UINT32 DeviceIdMappingIndex
;
535 } CM_ARM_SMMUV3_NODE
;
537 /** A structure that describes the
538 PMCG node for the Platform.
540 typedef struct CmArmPmcgNode
{
541 /// An unique token used to ideintify this object
542 CM_OBJECT_TOKEN Token
;
543 /// Number of ID mappings
544 UINT32 IdMappingCount
;
545 /// Reference token for the ID mapping array
546 CM_OBJECT_TOKEN IdMappingToken
;
548 /// Base Address for performance monitor counter group
550 /// GSIV for the Overflow interrupt
551 UINT32 OverflowInterrupt
;
552 /// Page 1 Base address
553 UINT64 Page1BaseAddress
;
555 /// Reference token for the IORT node associated with this node
556 CM_OBJECT_TOKEN ReferenceToken
;
559 /** A structure that describes the
560 ID Mappings for the Platform.
562 typedef struct CmArmIdMapping
{
565 /// Number of input IDs
569 /// Reference token for the output node
570 CM_OBJECT_TOKEN OutputReferenceToken
;
575 /** A structure that describes the
576 SMMU interrupts for the Platform.
578 typedef struct CmArmSmmuInterrupt
{
584 } CM_ARM_SMMU_INTERRUPT
;
588 #endif // ARM_NAMESPACE_OBJECTS_H_