DynamicTablesPkg/Include/ArmNameSpaceObjects.h

   1 /** @file
   2
   3   Copyright (c) 2017 - 2019, ARM Limited. All rights reserved.
   4
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7   @par Glossary:
   8     - Cm or CM   - Configuration Manager
   9     - Obj or OBJ - Object
  10     - Std or STD - Standard
  11 **/
  12
  13 #ifndef ARM_NAMESPACE_OBJECTS_H_
  14 #define ARM_NAMESPACE_OBJECTS_H_
  15
  16 #include <StandardNameSpaceObjects.h>
  17
  18 #pragma pack(1)
  19
  20 /** The EARM_OBJECT_ID enum describes the Object IDs
  21     in the ARM Namespace
  22 */
  23 typedef enum ArmObjectID {
  24   EArmObjReserved,                    ///<  0 - Reserved
  25   EArmObjBootArchInfo,                ///<  1 - Boot Architecture Info
  26   EArmObjCpuInfo,                     ///<  2 - CPU Info
  27   EArmObjPowerManagementProfileInfo,  ///<  3 - Power Management Profile Info
  28   EArmObjGicCInfo,                    ///<  4 - GIC CPU Interface Info
  29   EArmObjGicDInfo,                    ///<  5 - GIC Distributor Info
  30   EArmObjGicMsiFrameInfo,             ///<  6 - GIC MSI Frame Info
  31   EArmObjGicRedistributorInfo,        ///<  7 - GIC Redistributor Info
  32   EArmObjGicItsInfo,                  ///<  8 - GIC ITS Info
  33   EArmObjSerialConsolePortInfo,       ///<  9 - Serial Console Port Info
  34   EArmObjSerialDebugPortInfo,         ///< 10 - Serial Debug Port Info
  35   EArmObjGenericTimerInfo,            ///< 11 - Generic Timer Info
  36   EArmObjPlatformGTBlockInfo,         ///< 12 - Platform GT Block Info
  37   EArmObjGTBlockTimerFrameInfo,       ///< 13 - Generic Timer Block Frame Info
  38   EArmObjPlatformGenericWatchdogInfo, ///< 14 - Platform Generic Watchdog
  39   EArmObjPciConfigSpaceInfo,          ///< 15 - PCI Configuration Space Info
  40   EArmObjHypervisorVendorIdentity,    ///< 16 - Hypervisor Vendor Id
  41   EArmObjFixedFeatureFlags,           ///< 17 - Fixed feature flags for FADT
  42   EArmObjItsGroup,                    ///< 18 - ITS Group
  43   EArmObjNamedComponent,              ///< 19 - Named Component
  44   EArmObjRootComplex,                 ///< 20 - Root Complex
  45   EArmObjSmmuV1SmmuV2,                ///< 21 - SMMUv1 or SMMUv2
  46   EArmObjSmmuV3,                      ///< 22 - SMMUv3
  47   EArmObjPmcg,                        ///< 23 - PMCG
  48   EArmObjGicItsIdentifierArray,       ///< 24 - GIC ITS Identifier Array
  49   EArmObjIdMappingArray,              ///< 25 - ID Mapping Array
  50   EArmObjSmmuInterruptArray,          ///< 26 - SMMU Interrupt Array
  51   EArmObjProcHierarchyInfo,           ///< 27 - Processor Hierarchy Info
  52   EArmObjCacheInfo,                   ///< 28 - Cache Info
  53   EArmObjProcNodeIdInfo,              ///< 29 - Processor Hierarchy Node ID Info
  54   EArmObjCmRef,                       ///< 30 - CM Object Reference
  55   EArmObjMax
  56 } EARM_OBJECT_ID;
  57
  58 /** A structure that describes the
  59     ARM Boot Architecture flags.
  60
  61     ID: EArmObjBootArchInfo
  62 */
  63 typedef struct CmArmBootArchInfo {
  64   /** This is the ARM_BOOT_ARCH flags field of the FADT Table
  65       described in the ACPI Table Specification.
  66   */
  67   UINT32  BootArchFlags;
  68 } CM_ARM_BOOT_ARCH_INFO;
  69
  70 typedef struct CmArmCpuInfo {
  71   // Reserved for use when SMBIOS tables are implemented
  72 } CM_ARM_CPU_INFO;
  73
  74 /** A structure that describes the
  75     Power Management Profile Information for the Platform.
  76
  77     ID: EArmObjPowerManagementProfileInfo
  78 */
  79 typedef struct CmArmPowerManagementProfileInfo {
  80   /** This is the Preferred_PM_Profile field of the FADT Table
  81       described in the ACPI Specification
  82   */
  83   UINT8  PowerManagementProfile;
  84 } CM_ARM_POWER_MANAGEMENT_PROFILE_INFO;
  85
  86 /** A structure that describes the
  87     GIC CPU Interface for the Platform.
  88
  89     ID: EArmObjGicCInfo
  90 */
  91 typedef struct CmArmGicCInfo {
  92   /// The GIC CPU Interface number.
  93   UINT32  CPUInterfaceNumber;
  94
  95   /** The ACPI Processor UID. This must match the
  96       _UID of the CPU Device object information described
  97       in the DSDT/SSDT for the CPU.
  98   */
  99   UINT32  AcpiProcessorUid;
 100
 101   /** The flags field as described by the GICC structure
 102       in the ACPI Specification.
 103   */
 104   UINT32  Flags;
 105
 106   /** The parking protocol version field as described by
 107     the GICC structure in the ACPI Specification.
 108   */
 109   UINT32  ParkingProtocolVersion;
 110
 111   /** The Performance Interrupt field as described by
 112       the GICC structure in the ACPI Specification.
 113   */
 114   UINT32  PerformanceInterruptGsiv;
 115
 116   /** The CPU Parked address field as described by
 117       the GICC structure in the ACPI Specification.
 118   */
 119   UINT64  ParkedAddress;
 120
 121   /** The base address for the GIC CPU Interface
 122       as described by the GICC structure in the
 123       ACPI Specification.
 124   */
 125   UINT64  PhysicalBaseAddress;
 126
 127   /** The base address for GICV interface
 128       as described by the GICC structure in the
 129       ACPI Specification.
 130   */
 131   UINT64  GICV;
 132
 133   /** The base address for GICH interface
 134       as described by the GICC structure in the
 135       ACPI Specification.
 136   */
 137   UINT64  GICH;
 138
 139   /** The GICV maintenance interrupt
 140       as described by the GICC structure in the
 141       ACPI Specification.
 142   */
 143   UINT32  VGICMaintenanceInterrupt;
 144
 145   /** The base address for GICR interface
 146       as described by the GICC structure in the
 147       ACPI Specification.
 148   */
 149   UINT64  GICRBaseAddress;
 150
 151   /** The MPIDR for the CPU
 152       as described by the GICC structure in the
 153       ACPI Specification.
 154   */
 155   UINT64  MPIDR;
 156
 157   /** The Processor Power Efficiency class
 158       as described by the GICC structure in the
 159       ACPI Specification.
 160   */
 161   UINT8   ProcessorPowerEfficiencyClass;
 162
 163   /** Statistical Profiling Extension buffer overflow GSIV. Zero if
 164       unsupported by this processor. This field was introduced in
 165       ACPI 6.3 (MADT revision 5) and is therefore ignored when
 166       generating MADT revision 4 or lower.
 167   */
 168   UINT16  SpeOverflowInterrupt;
 169 } CM_ARM_GICC_INFO;
 170
 171 /** A structure that describes the
 172     GIC Distributor information for the Platform.
 173
 174     ID: EArmObjGicDInfo
 175 */
 176 typedef struct CmArmGicDInfo {
 177   /// The Physical Base address for the GIC Distributor.
 178   UINT64  PhysicalBaseAddress;
 179
 180   /** The global system interrupt
 181       number where this GIC Distributor's
 182       interrupt inputs start.
 183   */
 184   UINT32  SystemVectorBase;
 185
 186   /** The GIC version as described
 187       by the GICD structure in the
 188       ACPI Specification.
 189   */
 190   UINT8   GicVersion;
 191 } CM_ARM_GICD_INFO;
 192
 193 /** A structure that describes the
 194     GIC MSI Frame information for the Platform.
 195
 196     ID: EArmObjGicMsiFrameInfo
 197 */
 198 typedef struct CmArmGicMsiFrameInfo {
 199   /// The GIC MSI Frame ID
 200   UINT32  GicMsiFrameId;
 201
 202   /// The Physical base address for the MSI Frame
 203   UINT64  PhysicalBaseAddress;
 204
 205   /** The GIC MSI Frame flags
 206       as described by the GIC MSI frame
 207       structure in the ACPI Specification.
 208   */
 209   UINT32  Flags;
 210
 211   /// SPI Count used by this frame
 212   UINT16  SPICount;
 213
 214   /// SPI Base used by this frame
 215   UINT16  SPIBase;
 216 } CM_ARM_GIC_MSI_FRAME_INFO;
 217
 218 /** A structure that describes the
 219     GIC Redistributor information for the Platform.
 220
 221     ID: EArmObjGicRedistributorInfo
 222 */
 223 typedef struct CmArmGicRedistInfo {
 224   /** The physical address of a page range
 225       containing all GIC Redistributors.
 226   */
 227   UINT64  DiscoveryRangeBaseAddress;
 228
 229   /// Length of the GIC Redistributor Discovery page range
 230   UINT32  DiscoveryRangeLength;
 231 } CM_ARM_GIC_REDIST_INFO;
 232
 233 /** A structure that describes the
 234     GIC Interrupt Translation Service information for the Platform.
 235
 236     ID: EArmObjGicItsInfo
 237 */
 238 typedef struct CmArmGicItsInfo {
 239   /// The GIC ITS ID
 240   UINT32  GicItsId;
 241
 242   /// The physical address for the Interrupt Translation Service
 243   UINT64  PhysicalBaseAddress;
 244 } CM_ARM_GIC_ITS_INFO;
 245
 246 /** A structure that describes the
 247     Serial Port information for the Platform.
 248
 249     ID: EArmObjSerialConsolePortInfo or
 250         EArmObjSerialDebugPortInfo
 251 */
 252 typedef struct CmArmSerialPortInfo {
 253   /// The physical base address for the serial port
 254   UINT64  BaseAddress;
 255
 256   /// The serial port interrupt
 257   UINT32  Interrupt;
 258
 259   /// The serial port baud rate
 260   UINT64  BaudRate;
 261
 262   /// The serial port clock
 263   UINT32  Clock;
 264
 265   /// Serial Port subtype
 266   UINT16  PortSubtype;
 267 } CM_ARM_SERIAL_PORT_INFO;
 268
 269 /** A structure that describes the
 270     Generic Timer information for the Platform.
 271
 272     ID: EArmObjGenericTimerInfo
 273 */
 274 typedef struct CmArmGenericTimerInfo {
 275   /// The physical base address for the counter control frame
 276   UINT64  CounterControlBaseAddress;
 277
 278   /// The physical base address for the counter read frame
 279   UINT64  CounterReadBaseAddress;
 280
 281   /// The secure PL1 timer interrupt
 282   UINT32  SecurePL1TimerGSIV;
 283
 284   /// The secure PL1 timer flags
 285   UINT32  SecurePL1TimerFlags;
 286
 287   /// The non-secure PL1 timer interrupt
 288   UINT32  NonSecurePL1TimerGSIV;
 289
 290   /// The non-secure PL1 timer flags
 291   UINT32  NonSecurePL1TimerFlags;
 292
 293   /// The virtual timer interrupt
 294   UINT32  VirtualTimerGSIV;
 295
 296   /// The virtual timer flags
 297   UINT32  VirtualTimerFlags;
 298
 299   /// The non-secure PL2 timer interrupt
 300   UINT32  NonSecurePL2TimerGSIV;
 301
 302   /// The non-secure PL2 timer flags
 303   UINT32  NonSecurePL2TimerFlags;
 304
 305   /// GSIV for the virtual EL2 timer
 306   UINT32  VirtualPL2TimerGSIV;
 307
 308   /// Flags for the virtual EL2 timer
 309   UINT32  VirtualPL2TimerFlags;
 310 } CM_ARM_GENERIC_TIMER_INFO;
 311
 312 /** A structure that describes the
 313     Platform Generic Block Timer Frame information for the Platform.
 314
 315     ID: EArmObjGTBlockTimerFrameInfo
 316 */
 317 typedef struct CmArmGTBlockTimerFrameInfo {
 318   /// The Generic Timer frame number
 319   UINT8   FrameNumber;
 320
 321   /// The physical base address for the CntBase block
 322   UINT64  PhysicalAddressCntBase;
 323
 324   /// The physical base address for the CntEL0Base block
 325   UINT64  PhysicalAddressCntEL0Base;
 326
 327   /// The physical timer interrupt
 328   UINT32  PhysicalTimerGSIV;
 329
 330   /** The physical timer flags as described by the GT Block
 331       Timer frame Structure in the ACPI Specification.
 332   */
 333   UINT32  PhysicalTimerFlags;
 334
 335   /// The virtual timer interrupt
 336   UINT32  VirtualTimerGSIV;
 337
 338   /** The virtual timer flags as described by the GT Block
 339       Timer frame Structure in the ACPI Specification.
 340   */
 341   UINT32  VirtualTimerFlags;
 342
 343   /** The common timer flags as described by the GT Block
 344       Timer frame Structure in the ACPI Specification.
 345   */
 346   UINT32  CommonFlags;
 347 } CM_ARM_GTBLOCK_TIMER_FRAME_INFO;
 348
 349 /** A structure that describes the
 350     Platform Generic Block Timer information for the Platform.
 351
 352     ID: EArmObjPlatformGTBlockInfo
 353 */
 354 typedef struct CmArmGTBlockInfo {
 355   /// The physical base address for the GT Block Timer structure
 356   UINT64            GTBlockPhysicalAddress;
 357
 358   /// The number of timer frames implemented in the GT Block
 359   UINT32            GTBlockTimerFrameCount;
 360
 361   /// Reference token for the GT Block timer frame list
 362   CM_OBJECT_TOKEN   GTBlockTimerFrameToken;
 363 } CM_ARM_GTBLOCK_INFO;
 364
 365 /** A structure that describes the
 366     SBSA Generic Watchdog information for the Platform.
 367
 368     ID: EArmObjPlatformGenericWatchdogInfo
 369 */
 370 typedef struct CmArmGenericWatchdogInfo {
 371   /// The physical base address of the SBSA Watchdog control frame
 372   UINT64  ControlFrameAddress;
 373
 374   /// The physical base address of the SBSA Watchdog refresh frame
 375   UINT64  RefreshFrameAddress;
 376
 377   /// The watchdog interrupt
 378   UINT32  TimerGSIV;
 379
 380   /** The flags for the watchdog as described by the SBSA watchdog
 381       structure in the ACPI specification.
 382   */
 383   UINT32  Flags;
 384 } CM_ARM_GENERIC_WATCHDOG_INFO;
 385
 386 /** A structure that describes the
 387     PCI Configuration Space information for the Platform.
 388
 389     ID: EArmObjPciConfigSpaceInfo
 390 */
 391 typedef struct CmArmPciConfigSpaceInfo {
 392   /// The physical base address for the PCI segment
 393   UINT64  BaseAddress;
 394
 395   /// The PCI segment group number
 396   UINT16  PciSegmentGroupNumber;
 397
 398   /// The start bus number
 399   UINT8   StartBusNumber;
 400
 401   /// The end bus number
 402   UINT8   EndBusNumber;
 403 } CM_ARM_PCI_CONFIG_SPACE_INFO;
 404
 405 /** A structure that describes the
 406     Hypervisor Vendor ID information for the Platform.
 407
 408     ID: EArmObjHypervisorVendorIdentity
 409 */
 410 typedef struct CmArmHypervisorVendorId {
 411   /// The hypervisor Vendor ID
 412   UINT64  HypervisorVendorId;
 413 } CM_ARM_HYPERVISOR_VENDOR_ID;
 414
 415 /** A structure that describes the
 416     Fixed feature flags for the Platform.
 417
 418     ID: EArmObjFixedFeatureFlags
 419 */
 420 typedef struct CmArmFixedFeatureFlags {
 421   /// The Fixed feature flags
 422   UINT32  Flags;
 423 } CM_ARM_FIXED_FEATURE_FLAGS;
 424
 425 /** A structure that describes the
 426     ITS Group node for the Platform.
 427
 428     ID: EArmObjItsGroup
 429 */
 430 typedef struct CmArmItsGroupNode {
 431   /// An unique token used to identify this object
 432   CM_OBJECT_TOKEN   Token;
 433   /// The number of ITS identifiers in the ITS node
 434   UINT32            ItsIdCount;
 435   /// Reference token for the ITS identifier array
 436   CM_OBJECT_TOKEN   ItsIdToken;
 437 } CM_ARM_ITS_GROUP_NODE;
 438
 439 /** A structure that describes the
 440     GIC ITS Identifiers for an ITS Group node.
 441
 442     ID: EArmObjGicItsIdentifierArray
 443 */
 444 typedef struct CmArmGicItsIdentifier {
 445   /// The ITS Identifier
 446   UINT32  ItsId;
 447 } CM_ARM_ITS_IDENTIFIER;
 448
 449 /** A structure that describes the
 450     Named component node for the Platform.
 451
 452     ID: EArmObjNamedComponent
 453 */
 454 typedef struct CmArmNamedComponentNode {
 455   /// An unique token used to identify this object
 456   CM_OBJECT_TOKEN   Token;
 457   /// Number of ID mappings
 458   UINT32            IdMappingCount;
 459   /// Reference token for the ID mapping array
 460   CM_OBJECT_TOKEN   IdMappingToken;
 461
 462   /// Flags for the named component
 463   UINT32            Flags;
 464
 465   /// Memory access properties : Cache coherent attributes
 466   UINT32            CacheCoherent;
 467   /// Memory access properties : Allocation hints
 468   UINT8             AllocationHints;
 469   /// Memory access properties : Memory access flags
 470   UINT8             MemoryAccessFlags;
 471
 472   /// Memory access properties : Address size limit
 473   UINT8             AddressSizeLimit;
 474   /** ASCII Null terminated string with the full path to
 475       the entry in the namespace for this object.
 476   */
 477   CHAR8*            ObjectName;
 478 } CM_ARM_NAMED_COMPONENT_NODE;
 479
 480 /** A structure that describes the
 481     Root complex node for the Platform.
 482
 483     ID: EArmObjRootComplex
 484 */
 485 typedef struct CmArmRootComplexNode {
 486   /// An unique token used to identify this object
 487   CM_OBJECT_TOKEN   Token;
 488   /// Number of ID mappings
 489   UINT32            IdMappingCount;
 490   /// Reference token for the ID mapping array
 491   CM_OBJECT_TOKEN   IdMappingToken;
 492
 493   /// Memory access properties : Cache coherent attributes
 494   UINT32            CacheCoherent;
 495   /// Memory access properties : Allocation hints
 496   UINT8             AllocationHints;
 497   /// Memory access properties : Memory access flags
 498   UINT8             MemoryAccessFlags;
 499
 500   /// ATS attributes
 501   UINT32            AtsAttribute;
 502   /// PCI segment number
 503   UINT32            PciSegmentNumber;
 504   /// Memory address size limit
 505   UINT8             MemoryAddressSize;
 506 } CM_ARM_ROOT_COMPLEX_NODE;
 507
 508 /** A structure that describes the
 509     SMMUv1 or SMMUv2 node for the Platform.
 510
 511     ID: EArmObjSmmuV1SmmuV2
 512 */
 513 typedef struct CmArmSmmuV1SmmuV2Node {
 514   /// An unique token used to identify this object
 515   CM_OBJECT_TOKEN   Token;
 516   /// Number of ID mappings
 517   UINT32            IdMappingCount;
 518   /// Reference token for the ID mapping array
 519   CM_OBJECT_TOKEN   IdMappingToken;
 520
 521   /// SMMU Base Address
 522   UINT64            BaseAddress;
 523   /// Length of the memory range covered by the SMMU
 524   UINT64            Span;
 525   /// SMMU Model
 526   UINT32            Model;
 527   /// SMMU flags
 528   UINT32            Flags;
 529
 530   /// Number of context interrupts
 531   UINT32            ContextInterruptCount;
 532   /// Reference token for the context interrupt array
 533   CM_OBJECT_TOKEN   ContextInterruptToken;
 534
 535   /// Number of PMU interrupts
 536   UINT32            PmuInterruptCount;
 537   /// Reference token for the PMU interrupt array
 538   CM_OBJECT_TOKEN   PmuInterruptToken;
 539
 540   /// GSIV of the SMMU_NSgIrpt interrupt
 541   UINT32            SMMU_NSgIrpt;
 542   /// SMMU_NSgIrpt interrupt flags
 543   UINT32            SMMU_NSgIrptFlags;
 544   /// GSIV of the SMMU_NSgCfgIrpt interrupt
 545   UINT32            SMMU_NSgCfgIrpt;
 546   /// SMMU_NSgCfgIrpt interrupt flags
 547   UINT32            SMMU_NSgCfgIrptFlags;
 548 } CM_ARM_SMMUV1_SMMUV2_NODE;
 549
 550 /** A structure that describes the
 551     SMMUv3 node for the Platform.
 552
 553     ID: EArmObjSmmuV3
 554 */
 555 typedef struct CmArmSmmuV3Node {
 556   /// An unique token used to identify this object
 557   CM_OBJECT_TOKEN   Token;
 558   /// Number of ID mappings
 559   UINT32            IdMappingCount;
 560   /// Reference token for the ID mapping array
 561   CM_OBJECT_TOKEN   IdMappingToken;
 562
 563   /// SMMU Base Address
 564   UINT64    BaseAddress;
 565   /// SMMU flags
 566   UINT32            Flags;
 567   /// VATOS address
 568   UINT64            VatosAddress;
 569   /// Model
 570   UINT32            Model;
 571   /// GSIV of the Event interrupt if SPI based
 572   UINT32            EventInterrupt;
 573   /// PRI Interrupt if SPI based
 574   UINT32            PriInterrupt;
 575   /// GERR interrupt if GSIV based
 576   UINT32            GerrInterrupt;
 577   /// Sync interrupt if GSIV based
 578   UINT32            SyncInterrupt;
 579
 580   /// Proximity domain flag
 581   UINT32            ProximityDomain;
 582   /// Index into the array of ID mapping
 583   UINT32            DeviceIdMappingIndex;
 584 } CM_ARM_SMMUV3_NODE;
 585
 586 /** A structure that describes the
 587     PMCG node for the Platform.
 588
 589     ID: EArmObjPmcg
 590 */
 591 typedef struct CmArmPmcgNode {
 592   /// An unique token used to identify this object
 593   CM_OBJECT_TOKEN   Token;
 594   /// Number of ID mappings
 595   UINT32            IdMappingCount;
 596   /// Reference token for the ID mapping array
 597   CM_OBJECT_TOKEN   IdMappingToken;
 598
 599   /// Base Address for performance monitor counter group
 600   UINT64            BaseAddress;
 601   /// GSIV for the Overflow interrupt
 602   UINT32            OverflowInterrupt;
 603   /// Page 1 Base address
 604   UINT64            Page1BaseAddress;
 605
 606   /// Reference token for the IORT node associated with this node
 607   CM_OBJECT_TOKEN   ReferenceToken;
 608 } CM_ARM_PMCG_NODE;
 609
 610 /** A structure that describes the
 611     ID Mappings for the Platform.
 612
 613     ID: EArmObjIdMappingArray
 614 */
 615 typedef struct CmArmIdMapping {
 616   /// Input base
 617   UINT32           InputBase;
 618   /// Number of input IDs
 619   UINT32           NumIds;
 620   /// Output Base
 621   UINT32           OutputBase;
 622   /// Reference token for the output node
 623   CM_OBJECT_TOKEN  OutputReferenceToken;
 624   /// Flags
 625   UINT32    Flags;
 626 } CM_ARM_ID_MAPPING;
 627
 628 /** A structure that describes the
 629     SMMU interrupts for the Platform.
 630
 631     ID: EArmObjSmmuInterruptArray
 632 */
 633 typedef struct CmArmSmmuInterrupt {
 634   /// Interrupt number
 635   UINT32    Interrupt;
 636
 637   /// Flags
 638   UINT32    Flags;
 639 } CM_ARM_SMMU_INTERRUPT;
 640
 641 /** A structure that describes the Processor Hierarchy Node (Type 0) in PPTT
 642
 643     ID: EArmObjProcHierarchyInfo
 644 */
 645 typedef struct CmArmProcHierarchyInfo {
 646   /// A unique token used to identify this object
 647   CM_OBJECT_TOKEN   Token;
 648   /// Processor structure flags (ACPI 6.3 - January 2019, PPTT, Table 5-155)
 649   UINT32            Flags;
 650   /// Token for the parent CM_ARM_PROC_HIERARCHY_INFO object in the processor
 651   /// topology. A value of CM_NULL_TOKEN means this node has no parent.
 652   CM_OBJECT_TOKEN   ParentToken;
 653   /// Token of the associated CM_ARM_GICC_INFO object which has the
 654   /// corresponding ACPI Processor ID. A value of CM_NULL_TOKEN means this
 655   /// node represents a group of associated processors and it does not have an
 656   /// associated GIC CPU interface.
 657   CM_OBJECT_TOKEN   GicCToken;
 658   /// Number of resources private to this Node
 659   UINT32            NoOfPrivateResources;
 660   /// Token of the array which contains references to the resources private to
 661   /// this CM_ARM_PROC_HIERARCHY_INFO instance. This field is ignored if
 662   /// the NoOfPrivateResources is 0, in which case it is recomended to set
 663   /// this field to CM_NULL_TOKEN.
 664   CM_OBJECT_TOKEN   PrivateResourcesArrayToken;
 665 } CM_ARM_PROC_HIERARCHY_INFO;
 666
 667 /** A structure that describes the Cache Type Structure (Type 1) in PPTT
 668
 669     ID: EArmObjCacheInfo
 670 */
 671 typedef struct CmArmCacheInfo {
 672   /// A unique token used to identify this object
 673   CM_OBJECT_TOKEN   Token;
 674   /// Reference token for the next level of cache that is private to the same
 675   /// CM_ARM_PROC_HIERARCHY_INFO instance. A value of CM_NULL_TOKEN means this
 676   /// entry represents the last cache level appropriate to the processor
 677   /// hierarchy node structures using this entry.
 678   CM_OBJECT_TOKEN   NextLevelOfCacheToken;
 679   /// Size of the cache in bytes
 680   UINT32            Size;
 681   /// Number of sets in the cache
 682   UINT32            NumberOfSets;
 683   /// Integer number of ways. The maximum associativity supported by
 684   /// ACPI Cache type structure is limited to MAX_UINT8. However,
 685   /// the maximum number of ways supported by the architecture is
 686   /// PPTT_ARM_CCIDX_CACHE_ASSOCIATIVITY_MAX. Therfore this field
 687   /// is 32-bit wide.
 688   UINT32            Associativity;
 689   /// Cache attributes (ACPI 6.3 - January 2019, PPTT, Table 5-156)
 690   UINT8             Attributes;
 691   /// Line size in bytes
 692   UINT16            LineSize;
 693 } CM_ARM_CACHE_INFO;
 694
 695 /** A structure that describes the ID Structure (Type 2) in PPTT
 696
 697     ID: EArmObjProcNodeIdInfo
 698 */
 699 typedef struct CmArmProcNodeIdInfo {
 700   /// A unique token used to identify this object
 701   CM_OBJECT_TOKEN   Token;
 702   // Vendor ID (as described in ACPI ID registry)
 703   UINT32            VendorId;
 704   /// First level unique node ID
 705   UINT64            Level1Id;
 706   /// Second level unique node ID
 707   UINT64            Level2Id;
 708   /// Major revision of the node
 709   UINT16            MajorRev;
 710   /// Minor revision of the node
 711   UINT16            MinorRev;
 712   /// Spin revision of the node
 713   UINT16            SpinRev;
 714 } CM_ARM_PROC_NODE_ID_INFO;
 715
 716 /** A structure that describes a reference to another Configuration Manager
 717     object.
 718
 719     This is useful for creating an array of reference tokens. The framework
 720     can then query the configuration manager for these arrays using the
 721     object ID EArmObjCmRef.
 722
 723     This can be used is to represent one-to-many relationships between objects.
 724
 725     ID: EArmObjCmRef
 726 */
 727 typedef struct CmArmObjRef {
 728   /// Token of the CM object being referenced
 729   CM_OBJECT_TOKEN   ReferenceToken;
 730 } CM_ARM_OBJ_REF;
 731
 732 #pragma pack()
 733
 734 #endif // ARM_NAMESPACE_OBJECTS_H_