DynamicTablesPkg/Include/ArmNameSpaceObjects.h

   1 /** @file
   2
   3   Copyright (c) 2017 - 2019, ARM Limited. All rights reserved.
   4
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7   @par Glossary:
   8     - Cm or CM   - Configuration Manager
   9     - Obj or OBJ - Object
  10     - Std or STD - Standard
  11 **/
  12
  13 #ifndef ARM_NAMESPACE_OBJECTS_H_
  14 #define ARM_NAMESPACE_OBJECTS_H_
  15
  16 #include <StandardNameSpaceObjects.h>
  17
  18 #pragma pack(1)
  19
  20 /** The EARM_OBJECT_ID enum describes the Object IDs
  21     in the ARM Namespace
  22 */
  23 typedef enum ArmObjectID {
  24   EArmObjReserved,                    ///<  0 - Reserved
  25   EArmObjBootArchInfo,                ///<  1 - Boot Architecture Info
  26   EArmObjCpuInfo,                     ///<  2 - CPU Info
  27   EArmObjPowerManagementProfileInfo,  ///<  3 - Power Management Profile Info
  28   EArmObjGicCInfo,                    ///<  4 - GIC CPU Interface Info
  29   EArmObjGicDInfo,                    ///<  5 - GIC Distributor Info
  30   EArmObjGicMsiFrameInfo,             ///<  6 - GIC MSI Frame Info
  31   EArmObjGicRedistributorInfo,        ///<  7 - GIC Redistributor Info
  32   EArmObjGicItsInfo,                  ///<  8 - GIC ITS Info
  33   EArmObjSerialConsolePortInfo,       ///<  9 - Serial Console Port Info
  34   EArmObjSerialDebugPortInfo,         ///< 10 - Serial Debug Port Info
  35   EArmObjGenericTimerInfo,            ///< 11 - Generic Timer Info
  36   EArmObjPlatformGTBlockInfo,         ///< 12 - Platform GT Block Info
  37   EArmObjGTBlockTimerFrameInfo,       ///< 13 - Generic Timer Block Frame Info
  38   EArmObjPlatformGenericWatchdogInfo, ///< 14 - Platform Generic Watchdog
  39   EArmObjPciConfigSpaceInfo,          ///< 15 - PCI Configuration Space Info
  40   EArmObjHypervisorVendorIdentity,    ///< 16 - Hypervisor Vendor Id
  41   EArmObjFixedFeatureFlags,           ///< 17 - Fixed feature flags for FADT
  42   EArmObjItsGroup,                    ///< 18 - ITS Group
  43   EArmObjNamedComponent,              ///< 19 - Named Component
  44   EArmObjRootComplex,                 ///< 20 - Root Complex
  45   EArmObjSmmuV1SmmuV2,                ///< 21 - SMMUv1 or SMMUv2
  46   EArmObjSmmuV3,                      ///< 22 - SMMUv3
  47   EArmObjPmcg,                        ///< 23 - PMCG
  48   EArmObjGicItsIdentifierArray,       ///< 24 - GIC ITS Identifier Array
  49   EArmObjIdMappingArray,              ///< 25 - ID Mapping Array
  50   EArmObjSmmuInterruptArray,          ///< 26 - SMMU Interrupt Array
  51   EArmObjMax
  52 } EARM_OBJECT_ID;
  53
  54 /** A structure that describes the
  55     ARM Boot Architecture flags.
  56
  57     ID: EArmObjBootArchInfo
  58 */
  59 typedef struct CmArmBootArchInfo {
  60   /** This is the ARM_BOOT_ARCH flags field of the FADT Table
  61       described in the ACPI Table Specification.
  62   */
  63   UINT32  BootArchFlags;
  64 } CM_ARM_BOOT_ARCH_INFO;
  65
  66 typedef struct CmArmCpuInfo {
  67   // Reserved for use when SMBIOS tables are implemented
  68 } CM_ARM_CPU_INFO;
  69
  70 /** A structure that describes the
  71     Power Management Profile Information for the Platform.
  72
  73     ID: EArmObjPowerManagementProfileInfo
  74 */
  75 typedef struct CmArmPowerManagementProfileInfo {
  76   /** This is the Preferred_PM_Profile field of the FADT Table
  77       described in the ACPI Specification
  78   */
  79   UINT8  PowerManagementProfile;
  80 } CM_ARM_POWER_MANAGEMENT_PROFILE_INFO;
  81
  82 /** A structure that describes the
  83     GIC CPU Interface for the Platform.
  84
  85     ID: EArmObjGicCInfo
  86 */
  87 typedef struct CmArmGicCInfo {
  88   /// The GIC CPU Interface number.
  89   UINT32  CPUInterfaceNumber;
  90
  91   /** The ACPI Processor UID. This must match the
  92       _UID of the CPU Device object information described
  93       in the DSDT/SSDT for the CPU.
  94   */
  95   UINT32  AcpiProcessorUid;
  96
  97   /** The flags field as described by the GICC structure
  98       in the ACPI Specification.
  99   */
 100   UINT32  Flags;
 101
 102   /** The parking protocol version field as described by
 103     the GICC structure in the ACPI Specification.
 104   */
 105   UINT32  ParkingProtocolVersion;
 106
 107   /** The Performance Interrupt field as described by
 108       the GICC structure in the ACPI Specification.
 109   */
 110   UINT32  PerformanceInterruptGsiv;
 111
 112   /** The CPU Parked address field as described by
 113       the GICC structure in the ACPI Specification.
 114   */
 115   UINT64  ParkedAddress;
 116
 117   /** The base address for the GIC CPU Interface
 118       as described by the GICC structure in the
 119       ACPI Specification.
 120   */
 121   UINT64  PhysicalBaseAddress;
 122
 123   /** The base address for GICV interface
 124       as described by the GICC structure in the
 125       ACPI Specification.
 126   */
 127   UINT64  GICV;
 128
 129   /** The base address for GICH interface
 130       as described by the GICC structure in the
 131       ACPI Specification.
 132   */
 133   UINT64  GICH;
 134
 135   /** The GICV maintenance interrupt
 136       as described by the GICC structure in the
 137       ACPI Specification.
 138   */
 139   UINT32  VGICMaintenanceInterrupt;
 140
 141   /** The base address for GICR interface
 142       as described by the GICC structure in the
 143       ACPI Specification.
 144   */
 145   UINT64  GICRBaseAddress;
 146
 147   /** The MPIDR for the CPU
 148       as described by the GICC structure in the
 149       ACPI Specification.
 150   */
 151   UINT64  MPIDR;
 152
 153   /** The Processor Power Efficiency class
 154       as described by the GICC structure in the
 155       ACPI Specification.
 156   */
 157   UINT8   ProcessorPowerEfficiencyClass;
 158 } CM_ARM_GICC_INFO;
 159
 160 /** A structure that describes the
 161     GIC Distributor information for the Platform.
 162
 163     ID: EArmObjGicDInfo
 164 */
 165 typedef struct CmArmGicDInfo {
 166   /// The Physical Base address for the GIC Distributor.
 167   UINT64  PhysicalBaseAddress;
 168
 169   /** The global system interrupt
 170       number where this GIC Distributor's
 171       interrupt inputs start.
 172   */
 173   UINT32  SystemVectorBase;
 174
 175   /** The GIC version as described
 176       by the GICD structure in the
 177       ACPI Specification.
 178   */
 179   UINT8   GicVersion;
 180 } CM_ARM_GICD_INFO;
 181
 182 /** A structure that describes the
 183     GIC MSI Frame information for the Platform.
 184
 185     ID: EArmObjGicMsiFrameInfo
 186 */
 187 typedef struct CmArmGicMsiFrameInfo {
 188   /// The GIC MSI Frame ID
 189   UINT32  GicMsiFrameId;
 190
 191   /// The Physical base address for the MSI Frame
 192   UINT64  PhysicalBaseAddress;
 193
 194   /** The GIC MSI Frame flags
 195       as described by the GIC MSI frame
 196       structure in the ACPI Specification.
 197   */
 198   UINT32  Flags;
 199
 200   /// SPI Count used by this frame
 201   UINT16  SPICount;
 202
 203   /// SPI Base used by this frame
 204   UINT16  SPIBase;
 205 } CM_ARM_GIC_MSI_FRAME_INFO;
 206
 207 /** A structure that describes the
 208     GIC Redistributor information for the Platform.
 209
 210     ID: EArmObjGicRedistributorInfo
 211 */
 212 typedef struct CmArmGicRedistInfo {
 213   /** The physical address of a page range
 214       containing all GIC Redistributors.
 215   */
 216   UINT64  DiscoveryRangeBaseAddress;
 217
 218   /// Length of the GIC Redistributor Discovery page range
 219   UINT32  DiscoveryRangeLength;
 220 } CM_ARM_GIC_REDIST_INFO;
 221
 222 /** A structure that describes the
 223     GIC Interrupt Translation Service information for the Platform.
 224
 225     ID: EArmObjGicItsInfo
 226 */
 227 typedef struct CmArmGicItsInfo {
 228   /// The GIC ITS ID
 229   UINT32  GicItsId;
 230
 231   /// The physical address for the Interrupt Translation Service
 232   UINT64  PhysicalBaseAddress;
 233 } CM_ARM_GIC_ITS_INFO;
 234
 235 /** A structure that describes the
 236     Serial Port information for the Platform.
 237
 238     ID: EArmObjSerialConsolePortInfo or
 239         EArmObjSerialDebugPortInfo
 240 */
 241 typedef struct CmArmSerialPortInfo {
 242   /// The physical base address for the serial port
 243   UINT64  BaseAddress;
 244
 245   /// The serial port interrupt
 246   UINT32  Interrupt;
 247
 248   /// The serial port baud rate
 249   UINT64  BaudRate;
 250
 251   /// The serial port clock
 252   UINT32  Clock;
 253
 254   /// Serial Port subtype
 255   UINT16  PortSubtype;
 256 } CM_ARM_SERIAL_PORT_INFO;
 257
 258 /** A structure that describes the
 259     Generic Timer information for the Platform.
 260
 261     ID: EArmObjGenericTimerInfo
 262 */
 263 typedef struct CmArmGenericTimerInfo {
 264   /// The physical base address for the counter control frame
 265   UINT64  CounterControlBaseAddress;
 266
 267   /// The physical base address for the counter read frame
 268   UINT64  CounterReadBaseAddress;
 269
 270   /// The secure PL1 timer interrupt
 271   UINT32  SecurePL1TimerGSIV;
 272
 273   /// The secure PL1 timer flags
 274   UINT32  SecurePL1TimerFlags;
 275
 276   /// The non-secure PL1 timer interrupt
 277   UINT32  NonSecurePL1TimerGSIV;
 278
 279   /// The non-secure PL1 timer flags
 280   UINT32  NonSecurePL1TimerFlags;
 281
 282   /// The virtual timer interrupt
 283   UINT32  VirtualTimerGSIV;
 284
 285   /// The virtual timer flags
 286   UINT32  VirtualTimerFlags;
 287
 288   /// The non-secure PL2 timer interrupt
 289   UINT32  NonSecurePL2TimerGSIV;
 290
 291   /// The non-secure PL2 timer flags
 292   UINT32  NonSecurePL2TimerFlags;
 293 } CM_ARM_GENERIC_TIMER_INFO;
 294
 295 /** A structure that describes the
 296     Platform Generic Block Timer Frame information for the Platform.
 297
 298     ID: EArmObjGTBlockTimerFrameInfo
 299 */
 300 typedef struct CmArmGTBlockTimerFrameInfo {
 301   /// The Generic Timer frame number
 302   UINT8   FrameNumber;
 303
 304   /// The physical base address for the CntBase block
 305   UINT64  PhysicalAddressCntBase;
 306
 307   /// The physical base address for the CntEL0Base block
 308   UINT64  PhysicalAddressCntEL0Base;
 309
 310   /// The physical timer interrupt
 311   UINT32  PhysicalTimerGSIV;
 312
 313   /** The physical timer flags as described by the GT Block
 314       Timer frame Structure in the ACPI Specification.
 315   */
 316   UINT32  PhysicalTimerFlags;
 317
 318   /// The virtual timer interrupt
 319   UINT32  VirtualTimerGSIV;
 320
 321   /** The virtual timer flags as described by the GT Block
 322       Timer frame Structure in the ACPI Specification.
 323   */
 324   UINT32  VirtualTimerFlags;
 325
 326   /** The common timer flags as described by the GT Block
 327       Timer frame Structure in the ACPI Specification.
 328   */
 329   UINT32  CommonFlags;
 330 } CM_ARM_GTBLOCK_TIMER_FRAME_INFO;
 331
 332 /** A structure that describes the
 333     Platform Generic Block Timer information for the Platform.
 334
 335     ID: EArmObjPlatformGTBlockInfo
 336 */
 337 typedef struct CmArmGTBlockInfo {
 338   /// The physical base address for the GT Block Timer structure
 339   UINT64            GTBlockPhysicalAddress;
 340
 341   /// The number of timer frames implemented in the GT Block
 342   UINT32            GTBlockTimerFrameCount;
 343
 344   /// Reference token for the GT Block timer frame list
 345   CM_OBJECT_TOKEN   GTBlockTimerFrameToken;
 346 } CM_ARM_GTBLOCK_INFO;
 347
 348 /** A structure that describes the
 349     SBSA Generic Watchdog information for the Platform.
 350
 351     ID: EArmObjPlatformGenericWatchdogInfo
 352 */
 353 typedef struct CmArmGenericWatchdogInfo {
 354   /// The physical base address of the SBSA Watchdog control frame
 355   UINT64  ControlFrameAddress;
 356
 357   /// The physical base address of the SBSA Watchdog refresh frame
 358   UINT64  RefreshFrameAddress;
 359
 360   /// The watchdog interrupt
 361   UINT32  TimerGSIV;
 362
 363   /** The flags for the watchdog as described by the SBSA watchdog
 364       structure in the ACPI specification.
 365   */
 366   UINT32  Flags;
 367 } CM_ARM_GENERIC_WATCHDOG_INFO;
 368
 369 /** A structure that describes the
 370     PCI Configuration Space information for the Platform.
 371
 372     ID: EArmObjPciConfigSpaceInfo
 373 */
 374 typedef struct CmArmPciConfigSpaceInfo {
 375   /// The physical base address for the PCI segment
 376   UINT64  BaseAddress;
 377
 378   /// The PCI segment group number
 379   UINT16  PciSegmentGroupNumber;
 380
 381   /// The start bus number
 382   UINT8   StartBusNumber;
 383
 384   /// The end bus number
 385   UINT8   EndBusNumber;
 386 } CM_ARM_PCI_CONFIG_SPACE_INFO;
 387
 388 /** A structure that describes the
 389     Hypervisor Vendor ID information for the Platform.
 390
 391     ID: EArmObjHypervisorVendorIdentity
 392 */
 393 typedef struct CmArmHypervisorVendorId {
 394   /// The hypervisor Vendor ID
 395   UINT64  HypervisorVendorId;
 396 } CM_ARM_HYPERVISOR_VENDOR_ID;
 397
 398 /** A structure that describes the
 399     Fixed feature flags for the Platform.
 400
 401     ID: EArmObjFixedFeatureFlags
 402 */
 403 typedef struct CmArmFixedFeatureFlags {
 404   /// The Fixed feature flags
 405   UINT32  Flags;
 406 } CM_ARM_FIXED_FEATURE_FLAGS;
 407
 408 /** A structure that describes the
 409     ITS Group node for the Platform.
 410
 411     ID: EArmObjItsGroup
 412 */
 413 typedef struct CmArmItsGroupNode {
 414   /// An unique token used to identify this object
 415   CM_OBJECT_TOKEN   Token;
 416   /// The number of ITS identifiers in the ITS node
 417   UINT32            ItsIdCount;
 418   /// Reference token for the ITS identifier array
 419   CM_OBJECT_TOKEN   ItsIdToken;
 420 } CM_ARM_ITS_GROUP_NODE;
 421
 422 /** A structure that describes the
 423     GIC ITS Identifiers for an ITS Group node.
 424
 425     ID: EArmObjGicItsIdentifierArray
 426 */
 427 typedef struct CmArmGicItsIdentifier {
 428   /// The ITS Identifier
 429   UINT32  ItsId;
 430 } CM_ARM_ITS_IDENTIFIER;
 431
 432 /** A structure that describes the
 433     Named component node for the Platform.
 434
 435     ID: EArmObjNamedComponent
 436 */
 437 typedef struct CmArmNamedComponentNode {
 438   /// An unique token used to identify this object
 439   CM_OBJECT_TOKEN   Token;
 440   /// Number of ID mappings
 441   UINT32            IdMappingCount;
 442   /// Reference token for the ID mapping array
 443   CM_OBJECT_TOKEN   IdMappingToken;
 444
 445   /// Flags for the named component
 446   UINT32            Flags;
 447
 448   /// Memory access properties : Cache coherent attributes
 449   UINT32            CacheCoherent;
 450   /// Memory access properties : Allocation hints
 451   UINT8             AllocationHints;
 452   /// Memory access properties : Memory access flags
 453   UINT8             MemoryAccessFlags;
 454
 455   /// Memory access properties : Address size limit
 456   UINT8             AddressSizeLimit;
 457   /** ASCII Null terminated string with the full path to
 458       the entry in the namespace for this object.
 459   */
 460   CHAR8*            ObjectName;
 461 } CM_ARM_NAMED_COMPONENT_NODE;
 462
 463 /** A structure that describes the
 464     Root complex node for the Platform.
 465
 466     ID: EArmObjRootComplex
 467 */
 468 typedef struct CmArmRootComplexNode {
 469   /// An unique token used to identify this object
 470   CM_OBJECT_TOKEN   Token;
 471   /// Number of ID mappings
 472   UINT32            IdMappingCount;
 473   /// Reference token for the ID mapping array
 474   CM_OBJECT_TOKEN   IdMappingToken;
 475
 476   /// Memory access properties : Cache coherent attributes
 477   UINT32            CacheCoherent;
 478   /// Memory access properties : Allocation hints
 479   UINT8             AllocationHints;
 480   /// Memory access properties : Memory access flags
 481   UINT8             MemoryAccessFlags;
 482
 483   /// ATS attributes
 484   UINT32            AtsAttribute;
 485   /// PCI segment number
 486   UINT32            PciSegmentNumber;
 487   /// Memory address size limit
 488   UINT8             MemoryAddressSize;
 489 } CM_ARM_ROOT_COMPLEX_NODE;
 490
 491 /** A structure that describes the
 492     SMMUv1 or SMMUv2 node for the Platform.
 493
 494     ID: EArmObjSmmuV1SmmuV2
 495 */
 496 typedef struct CmArmSmmuV1SmmuV2Node {
 497   /// An unique token used to identify this object
 498   CM_OBJECT_TOKEN   Token;
 499   /// Number of ID mappings
 500   UINT32            IdMappingCount;
 501   /// Reference token for the ID mapping array
 502   CM_OBJECT_TOKEN   IdMappingToken;
 503
 504   /// SMMU Base Address
 505   UINT64            BaseAddress;
 506   /// Length of the memory range covered by the SMMU
 507   UINT64            Span;
 508   /// SMMU Model
 509   UINT32            Model;
 510   /// SMMU flags
 511   UINT32            Flags;
 512
 513   /// Number of context interrupts
 514   UINT32            ContextInterruptCount;
 515   /// Reference token for the context interrupt array
 516   CM_OBJECT_TOKEN   ContextInterruptToken;
 517
 518   /// Number of PMU interrupts
 519   UINT32            PmuInterruptCount;
 520   /// Reference token for the PMU interrupt array
 521   CM_OBJECT_TOKEN   PmuInterruptToken;
 522
 523   /// GSIV of the SMMU_NSgIrpt interrupt
 524   UINT32            SMMU_NSgIrpt;
 525   /// SMMU_NSgIrpt interrupt flags
 526   UINT32            SMMU_NSgIrptFlags;
 527   /// GSIV of the SMMU_NSgCfgIrpt interrupt
 528   UINT32            SMMU_NSgCfgIrpt;
 529   /// SMMU_NSgCfgIrpt interrupt flags
 530   UINT32            SMMU_NSgCfgIrptFlags;
 531 } CM_ARM_SMMUV1_SMMUV2_NODE;
 532
 533 /** A structure that describes the
 534     SMMUv3 node for the Platform.
 535
 536     ID: EArmObjSmmuV3
 537 */
 538 typedef struct CmArmSmmuV3Node {
 539   /// An unique token used to identify this object
 540   CM_OBJECT_TOKEN   Token;
 541   /// Number of ID mappings
 542   UINT32            IdMappingCount;
 543   /// Reference token for the ID mapping array
 544   CM_OBJECT_TOKEN   IdMappingToken;
 545
 546   /// SMMU Base Address
 547   UINT64    BaseAddress;
 548   /// SMMU flags
 549   UINT32            Flags;
 550   /// VATOS address
 551   UINT64            VatosAddress;
 552   /// Model
 553   UINT32            Model;
 554   /// GSIV of the Event interrupt if SPI based
 555   UINT32            EventInterrupt;
 556   /// PRI Interrupt if SPI based
 557   UINT32            PriInterrupt;
 558   /// GERR interrupt if GSIV based
 559   UINT32            GerrInterrupt;
 560   /// Sync interrupt if GSIV based
 561   UINT32            SyncInterrupt;
 562
 563   /// Proximity domain flag
 564   UINT32            ProximityDomain;
 565   /// Index into the array of ID mapping
 566   UINT32            DeviceIdMappingIndex;
 567 } CM_ARM_SMMUV3_NODE;
 568
 569 /** A structure that describes the
 570     PMCG node for the Platform.
 571
 572     ID: EArmObjPmcg
 573 */
 574 typedef struct CmArmPmcgNode {
 575   /// An unique token used to identify this object
 576   CM_OBJECT_TOKEN   Token;
 577   /// Number of ID mappings
 578   UINT32            IdMappingCount;
 579   /// Reference token for the ID mapping array
 580   CM_OBJECT_TOKEN   IdMappingToken;
 581
 582   /// Base Address for performance monitor counter group
 583   UINT64            BaseAddress;
 584   /// GSIV for the Overflow interrupt
 585   UINT32            OverflowInterrupt;
 586   /// Page 1 Base address
 587   UINT64            Page1BaseAddress;
 588
 589   /// Reference token for the IORT node associated with this node
 590   CM_OBJECT_TOKEN   ReferenceToken;
 591 } CM_ARM_PMCG_NODE;
 592
 593 /** A structure that describes the
 594     ID Mappings for the Platform.
 595
 596     ID: EArmObjIdMappingArray
 597 */
 598 typedef struct CmArmIdMapping {
 599   /// Input base
 600   UINT32           InputBase;
 601   /// Number of input IDs
 602   UINT32           NumIds;
 603   /// Output Base
 604   UINT32           OutputBase;
 605   /// Reference token for the output node
 606   CM_OBJECT_TOKEN  OutputReferenceToken;
 607   /// Flags
 608   UINT32    Flags;
 609 } CM_ARM_ID_MAPPING;
 610
 611 /** A structure that describes the
 612     SMMU interrupts for the Platform.
 613
 614     ID: EArmObjSmmuInterruptArray
 615 */
 616 typedef struct CmArmSmmuInterrupt {
 617   /// Interrupt number
 618   UINT32    Interrupt;
 619
 620   /// Flags
 621   UINT32    Flags;
 622 } CM_ARM_SMMU_INTERRUPT;
 623
 624 #pragma pack()
 625
 626 #endif // ARM_NAMESPACE_OBJECTS_H_