DynamicTablesPkg/Include/ArmNameSpaceObjects.h

   1 /** @file
   2
   3   Copyright (c) 2017 - 2019, ARM Limited. All rights reserved.
   4
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7   @par Glossary:
   8     - Cm or CM   - Configuration Manager
   9     - Obj or OBJ - Object
  10     - Std or STD - Standard
  11 **/
  12
  13 #ifndef ARM_NAMESPACE_OBJECTS_H_
  14 #define ARM_NAMESPACE_OBJECTS_H_
  15
  16 #include <StandardNameSpaceObjects.h>
  17
  18 #pragma pack(1)
  19
  20 /** The EARM_OBJECT_ID enum describes the Object IDs
  21     in the ARM Namespace
  22 */
  23 typedef enum ArmObjectID {
  24   EArmObjReserved,                    ///<  0 - Reserved
  25   EArmObjBootArchInfo,                ///<  1 - Boot Architecture Info
  26   EArmObjCpuInfo,                     ///<  2 - CPU Info
  27   EArmObjPowerManagementProfileInfo,  ///<  3 - Power Management Profile Info
  28   EArmObjGicCInfo,                    ///<  4 - GIC CPU Interface Info
  29   EArmObjGicDInfo,                    ///<  5 - GIC Distributor Info
  30   EArmObjGicMsiFrameInfo,             ///<  6 - GIC MSI Frame Info
  31   EArmObjGicRedistributorInfo,        ///<  7 - GIC Redistributor Info
  32   EArmObjGicItsInfo,                  ///<  8 - GIC ITS Info
  33   EArmObjSerialConsolePortInfo,       ///<  9 - Serial Console Port Info
  34   EArmObjSerialDebugPortInfo,         ///< 10 - Serial Debug Port Info
  35   EArmObjGenericTimerInfo,            ///< 11 - Generic Timer Info
  36   EArmObjPlatformGTBlockInfo,         ///< 12 - Platform GT Block Info
  37   EArmObjGTBlockTimerFrameInfo,       ///< 13 - Generic Timer Block Frame Info
  38   EArmObjPlatformGenericWatchdogInfo, ///< 14 - Platform Generic Watchdog
  39   EArmObjPciConfigSpaceInfo,          ///< 15 - PCI Configuration Space Info
  40   EArmObjHypervisorVendorIdentity,    ///< 16 - Hypervisor Vendor Id
  41   EArmObjFixedFeatureFlags,           ///< 17 - Fixed feature flags for FADT
  42   EArmObjItsGroup,                    ///< 18 - ITS Group
  43   EArmObjNamedComponent,              ///< 19 - Named Component
  44   EArmObjRootComplex,                 ///< 20 - Root Complex
  45   EArmObjSmmuV1SmmuV2,                ///< 21 - SMMUv1 or SMMUv2
  46   EArmObjSmmuV3,                      ///< 22 - SMMUv3
  47   EArmObjPmcg,                        ///< 23 - PMCG
  48   EArmObjGicItsIdentifierArray,       ///< 24 - GIC ITS Identifier Array
  49   EArmObjIdMappingArray,              ///< 25 - ID Mapping Array
  50   EArmObjSmmuInterruptArray,          ///< 26 - SMMU Interrupt Array
  51   EArmObjMax
  52 } EARM_OBJECT_ID;
  53
  54 /** A structure that describes the
  55     ARM Boot Architecture flags.
  56
  57     ID: EArmObjBootArchInfo
  58 */
  59 typedef struct CmArmBootArchInfo {
  60   /** This is the ARM_BOOT_ARCH flags field of the FADT Table
  61       described in the ACPI Table Specification.
  62   */
  63   UINT32  BootArchFlags;
  64 } CM_ARM_BOOT_ARCH_INFO;
  65
  66 typedef struct CmArmCpuInfo {
  67   // Reserved for use when SMBIOS tables are implemented
  68 } CM_ARM_CPU_INFO;
  69
  70 /** A structure that describes the
  71     Power Management Profile Information for the Platform.
  72
  73     ID: EArmObjPowerManagementProfileInfo
  74 */
  75 typedef struct CmArmPowerManagementProfileInfo {
  76   /** This is the Preferred_PM_Profile field of the FADT Table
  77       described in the ACPI Specification
  78   */
  79   UINT8  PowerManagementProfile;
  80 } CM_ARM_POWER_MANAGEMENT_PROFILE_INFO;
  81
  82 /** A structure that describes the
  83     GIC CPU Interface for the Platform.
  84
  85     ID: EArmObjGicCInfo
  86 */
  87 typedef struct CmArmGicCInfo {
  88   /// The GIC CPU Interface number.
  89   UINT32  CPUInterfaceNumber;
  90
  91   /** The ACPI Processor UID. This must match the
  92       _UID of the CPU Device object information described
  93       in the DSDT/SSDT for the CPU.
  94   */
  95   UINT32  AcpiProcessorUid;
  96
  97   /** The flags field as described by the GICC structure
  98       in the ACPI Specification.
  99   */
 100   UINT32  Flags;
 101
 102   /** The parking protocol version field as described by
 103     the GICC structure in the ACPI Specification.
 104   */
 105   UINT32  ParkingProtocolVersion;
 106
 107   /** The Performance Interrupt field as described by
 108       the GICC structure in the ACPI Specification.
 109   */
 110   UINT32  PerformanceInterruptGsiv;
 111
 112   /** The CPU Parked address field as described by
 113       the GICC structure in the ACPI Specification.
 114   */
 115   UINT64  ParkedAddress;
 116
 117   /** The base address for the GIC CPU Interface
 118       as described by the GICC structure in the
 119       ACPI Specification.
 120   */
 121   UINT64  PhysicalBaseAddress;
 122
 123   /** The base address for GICV interface
 124       as described by the GICC structure in the
 125       ACPI Specification.
 126   */
 127   UINT64  GICV;
 128
 129   /** The base address for GICH interface
 130       as described by the GICC structure in the
 131       ACPI Specification.
 132   */
 133   UINT64  GICH;
 134
 135   /** The GICV maintenance interrupt
 136       as described by the GICC structure in the
 137       ACPI Specification.
 138   */
 139   UINT32  VGICMaintenanceInterrupt;
 140
 141   /** The base address for GICR interface
 142       as described by the GICC structure in the
 143       ACPI Specification.
 144   */
 145   UINT64  GICRBaseAddress;
 146
 147   /** The MPIDR for the CPU
 148       as described by the GICC structure in the
 149       ACPI Specification.
 150   */
 151   UINT64  MPIDR;
 152
 153   /** The Processor Power Efficiency class
 154       as described by the GICC structure in the
 155       ACPI Specification.
 156   */
 157   UINT8   ProcessorPowerEfficiencyClass;
 158
 159   /** Statistical Profiling Extension buffer overflow GSIV. Zero if
 160       unsupported by this processor. This field was introduced in
 161       ACPI 6.3 (MADT revision 5) and is therefore ignored when
 162       generating MADT revision 4 or lower.
 163   */
 164   UINT16  SpeOverflowInterrupt;
 165 } CM_ARM_GICC_INFO;
 166
 167 /** A structure that describes the
 168     GIC Distributor information for the Platform.
 169
 170     ID: EArmObjGicDInfo
 171 */
 172 typedef struct CmArmGicDInfo {
 173   /// The Physical Base address for the GIC Distributor.
 174   UINT64  PhysicalBaseAddress;
 175
 176   /** The global system interrupt
 177       number where this GIC Distributor's
 178       interrupt inputs start.
 179   */
 180   UINT32  SystemVectorBase;
 181
 182   /** The GIC version as described
 183       by the GICD structure in the
 184       ACPI Specification.
 185   */
 186   UINT8   GicVersion;
 187 } CM_ARM_GICD_INFO;
 188
 189 /** A structure that describes the
 190     GIC MSI Frame information for the Platform.
 191
 192     ID: EArmObjGicMsiFrameInfo
 193 */
 194 typedef struct CmArmGicMsiFrameInfo {
 195   /// The GIC MSI Frame ID
 196   UINT32  GicMsiFrameId;
 197
 198   /// The Physical base address for the MSI Frame
 199   UINT64  PhysicalBaseAddress;
 200
 201   /** The GIC MSI Frame flags
 202       as described by the GIC MSI frame
 203       structure in the ACPI Specification.
 204   */
 205   UINT32  Flags;
 206
 207   /// SPI Count used by this frame
 208   UINT16  SPICount;
 209
 210   /// SPI Base used by this frame
 211   UINT16  SPIBase;
 212 } CM_ARM_GIC_MSI_FRAME_INFO;
 213
 214 /** A structure that describes the
 215     GIC Redistributor information for the Platform.
 216
 217     ID: EArmObjGicRedistributorInfo
 218 */
 219 typedef struct CmArmGicRedistInfo {
 220   /** The physical address of a page range
 221       containing all GIC Redistributors.
 222   */
 223   UINT64  DiscoveryRangeBaseAddress;
 224
 225   /// Length of the GIC Redistributor Discovery page range
 226   UINT32  DiscoveryRangeLength;
 227 } CM_ARM_GIC_REDIST_INFO;
 228
 229 /** A structure that describes the
 230     GIC Interrupt Translation Service information for the Platform.
 231
 232     ID: EArmObjGicItsInfo
 233 */
 234 typedef struct CmArmGicItsInfo {
 235   /// The GIC ITS ID
 236   UINT32  GicItsId;
 237
 238   /// The physical address for the Interrupt Translation Service
 239   UINT64  PhysicalBaseAddress;
 240 } CM_ARM_GIC_ITS_INFO;
 241
 242 /** A structure that describes the
 243     Serial Port information for the Platform.
 244
 245     ID: EArmObjSerialConsolePortInfo or
 246         EArmObjSerialDebugPortInfo
 247 */
 248 typedef struct CmArmSerialPortInfo {
 249   /// The physical base address for the serial port
 250   UINT64  BaseAddress;
 251
 252   /// The serial port interrupt
 253   UINT32  Interrupt;
 254
 255   /// The serial port baud rate
 256   UINT64  BaudRate;
 257
 258   /// The serial port clock
 259   UINT32  Clock;
 260
 261   /// Serial Port subtype
 262   UINT16  PortSubtype;
 263 } CM_ARM_SERIAL_PORT_INFO;
 264
 265 /** A structure that describes the
 266     Generic Timer information for the Platform.
 267
 268     ID: EArmObjGenericTimerInfo
 269 */
 270 typedef struct CmArmGenericTimerInfo {
 271   /// The physical base address for the counter control frame
 272   UINT64  CounterControlBaseAddress;
 273
 274   /// The physical base address for the counter read frame
 275   UINT64  CounterReadBaseAddress;
 276
 277   /// The secure PL1 timer interrupt
 278   UINT32  SecurePL1TimerGSIV;
 279
 280   /// The secure PL1 timer flags
 281   UINT32  SecurePL1TimerFlags;
 282
 283   /// The non-secure PL1 timer interrupt
 284   UINT32  NonSecurePL1TimerGSIV;
 285
 286   /// The non-secure PL1 timer flags
 287   UINT32  NonSecurePL1TimerFlags;
 288
 289   /// The virtual timer interrupt
 290   UINT32  VirtualTimerGSIV;
 291
 292   /// The virtual timer flags
 293   UINT32  VirtualTimerFlags;
 294
 295   /// The non-secure PL2 timer interrupt
 296   UINT32  NonSecurePL2TimerGSIV;
 297
 298   /// The non-secure PL2 timer flags
 299   UINT32  NonSecurePL2TimerFlags;
 300 } CM_ARM_GENERIC_TIMER_INFO;
 301
 302 /** A structure that describes the
 303     Platform Generic Block Timer Frame information for the Platform.
 304
 305     ID: EArmObjGTBlockTimerFrameInfo
 306 */
 307 typedef struct CmArmGTBlockTimerFrameInfo {
 308   /// The Generic Timer frame number
 309   UINT8   FrameNumber;
 310
 311   /// The physical base address for the CntBase block
 312   UINT64  PhysicalAddressCntBase;
 313
 314   /// The physical base address for the CntEL0Base block
 315   UINT64  PhysicalAddressCntEL0Base;
 316
 317   /// The physical timer interrupt
 318   UINT32  PhysicalTimerGSIV;
 319
 320   /** The physical timer flags as described by the GT Block
 321       Timer frame Structure in the ACPI Specification.
 322   */
 323   UINT32  PhysicalTimerFlags;
 324
 325   /// The virtual timer interrupt
 326   UINT32  VirtualTimerGSIV;
 327
 328   /** The virtual timer flags as described by the GT Block
 329       Timer frame Structure in the ACPI Specification.
 330   */
 331   UINT32  VirtualTimerFlags;
 332
 333   /** The common timer flags as described by the GT Block
 334       Timer frame Structure in the ACPI Specification.
 335   */
 336   UINT32  CommonFlags;
 337 } CM_ARM_GTBLOCK_TIMER_FRAME_INFO;
 338
 339 /** A structure that describes the
 340     Platform Generic Block Timer information for the Platform.
 341
 342     ID: EArmObjPlatformGTBlockInfo
 343 */
 344 typedef struct CmArmGTBlockInfo {
 345   /// The physical base address for the GT Block Timer structure
 346   UINT64            GTBlockPhysicalAddress;
 347
 348   /// The number of timer frames implemented in the GT Block
 349   UINT32            GTBlockTimerFrameCount;
 350
 351   /// Reference token for the GT Block timer frame list
 352   CM_OBJECT_TOKEN   GTBlockTimerFrameToken;
 353 } CM_ARM_GTBLOCK_INFO;
 354
 355 /** A structure that describes the
 356     SBSA Generic Watchdog information for the Platform.
 357
 358     ID: EArmObjPlatformGenericWatchdogInfo
 359 */
 360 typedef struct CmArmGenericWatchdogInfo {
 361   /// The physical base address of the SBSA Watchdog control frame
 362   UINT64  ControlFrameAddress;
 363
 364   /// The physical base address of the SBSA Watchdog refresh frame
 365   UINT64  RefreshFrameAddress;
 366
 367   /// The watchdog interrupt
 368   UINT32  TimerGSIV;
 369
 370   /** The flags for the watchdog as described by the SBSA watchdog
 371       structure in the ACPI specification.
 372   */
 373   UINT32  Flags;
 374 } CM_ARM_GENERIC_WATCHDOG_INFO;
 375
 376 /** A structure that describes the
 377     PCI Configuration Space information for the Platform.
 378
 379     ID: EArmObjPciConfigSpaceInfo
 380 */
 381 typedef struct CmArmPciConfigSpaceInfo {
 382   /// The physical base address for the PCI segment
 383   UINT64  BaseAddress;
 384
 385   /// The PCI segment group number
 386   UINT16  PciSegmentGroupNumber;
 387
 388   /// The start bus number
 389   UINT8   StartBusNumber;
 390
 391   /// The end bus number
 392   UINT8   EndBusNumber;
 393 } CM_ARM_PCI_CONFIG_SPACE_INFO;
 394
 395 /** A structure that describes the
 396     Hypervisor Vendor ID information for the Platform.
 397
 398     ID: EArmObjHypervisorVendorIdentity
 399 */
 400 typedef struct CmArmHypervisorVendorId {
 401   /// The hypervisor Vendor ID
 402   UINT64  HypervisorVendorId;
 403 } CM_ARM_HYPERVISOR_VENDOR_ID;
 404
 405 /** A structure that describes the
 406     Fixed feature flags for the Platform.
 407
 408     ID: EArmObjFixedFeatureFlags
 409 */
 410 typedef struct CmArmFixedFeatureFlags {
 411   /// The Fixed feature flags
 412   UINT32  Flags;
 413 } CM_ARM_FIXED_FEATURE_FLAGS;
 414
 415 /** A structure that describes the
 416     ITS Group node for the Platform.
 417
 418     ID: EArmObjItsGroup
 419 */
 420 typedef struct CmArmItsGroupNode {
 421   /// An unique token used to identify this object
 422   CM_OBJECT_TOKEN   Token;
 423   /// The number of ITS identifiers in the ITS node
 424   UINT32            ItsIdCount;
 425   /// Reference token for the ITS identifier array
 426   CM_OBJECT_TOKEN   ItsIdToken;
 427 } CM_ARM_ITS_GROUP_NODE;
 428
 429 /** A structure that describes the
 430     GIC ITS Identifiers for an ITS Group node.
 431
 432     ID: EArmObjGicItsIdentifierArray
 433 */
 434 typedef struct CmArmGicItsIdentifier {
 435   /// The ITS Identifier
 436   UINT32  ItsId;
 437 } CM_ARM_ITS_IDENTIFIER;
 438
 439 /** A structure that describes the
 440     Named component node for the Platform.
 441
 442     ID: EArmObjNamedComponent
 443 */
 444 typedef struct CmArmNamedComponentNode {
 445   /// An unique token used to identify this object
 446   CM_OBJECT_TOKEN   Token;
 447   /// Number of ID mappings
 448   UINT32            IdMappingCount;
 449   /// Reference token for the ID mapping array
 450   CM_OBJECT_TOKEN   IdMappingToken;
 451
 452   /// Flags for the named component
 453   UINT32            Flags;
 454
 455   /// Memory access properties : Cache coherent attributes
 456   UINT32            CacheCoherent;
 457   /// Memory access properties : Allocation hints
 458   UINT8             AllocationHints;
 459   /// Memory access properties : Memory access flags
 460   UINT8             MemoryAccessFlags;
 461
 462   /// Memory access properties : Address size limit
 463   UINT8             AddressSizeLimit;
 464   /** ASCII Null terminated string with the full path to
 465       the entry in the namespace for this object.
 466   */
 467   CHAR8*            ObjectName;
 468 } CM_ARM_NAMED_COMPONENT_NODE;
 469
 470 /** A structure that describes the
 471     Root complex node for the Platform.
 472
 473     ID: EArmObjRootComplex
 474 */
 475 typedef struct CmArmRootComplexNode {
 476   /// An unique token used to identify this object
 477   CM_OBJECT_TOKEN   Token;
 478   /// Number of ID mappings
 479   UINT32            IdMappingCount;
 480   /// Reference token for the ID mapping array
 481   CM_OBJECT_TOKEN   IdMappingToken;
 482
 483   /// Memory access properties : Cache coherent attributes
 484   UINT32            CacheCoherent;
 485   /// Memory access properties : Allocation hints
 486   UINT8             AllocationHints;
 487   /// Memory access properties : Memory access flags
 488   UINT8             MemoryAccessFlags;
 489
 490   /// ATS attributes
 491   UINT32            AtsAttribute;
 492   /// PCI segment number
 493   UINT32            PciSegmentNumber;
 494   /// Memory address size limit
 495   UINT8             MemoryAddressSize;
 496 } CM_ARM_ROOT_COMPLEX_NODE;
 497
 498 /** A structure that describes the
 499     SMMUv1 or SMMUv2 node for the Platform.
 500
 501     ID: EArmObjSmmuV1SmmuV2
 502 */
 503 typedef struct CmArmSmmuV1SmmuV2Node {
 504   /// An unique token used to identify this object
 505   CM_OBJECT_TOKEN   Token;
 506   /// Number of ID mappings
 507   UINT32            IdMappingCount;
 508   /// Reference token for the ID mapping array
 509   CM_OBJECT_TOKEN   IdMappingToken;
 510
 511   /// SMMU Base Address
 512   UINT64            BaseAddress;
 513   /// Length of the memory range covered by the SMMU
 514   UINT64            Span;
 515   /// SMMU Model
 516   UINT32            Model;
 517   /// SMMU flags
 518   UINT32            Flags;
 519
 520   /// Number of context interrupts
 521   UINT32            ContextInterruptCount;
 522   /// Reference token for the context interrupt array
 523   CM_OBJECT_TOKEN   ContextInterruptToken;
 524
 525   /// Number of PMU interrupts
 526   UINT32            PmuInterruptCount;
 527   /// Reference token for the PMU interrupt array
 528   CM_OBJECT_TOKEN   PmuInterruptToken;
 529
 530   /// GSIV of the SMMU_NSgIrpt interrupt
 531   UINT32            SMMU_NSgIrpt;
 532   /// SMMU_NSgIrpt interrupt flags
 533   UINT32            SMMU_NSgIrptFlags;
 534   /// GSIV of the SMMU_NSgCfgIrpt interrupt
 535   UINT32            SMMU_NSgCfgIrpt;
 536   /// SMMU_NSgCfgIrpt interrupt flags
 537   UINT32            SMMU_NSgCfgIrptFlags;
 538 } CM_ARM_SMMUV1_SMMUV2_NODE;
 539
 540 /** A structure that describes the
 541     SMMUv3 node for the Platform.
 542
 543     ID: EArmObjSmmuV3
 544 */
 545 typedef struct CmArmSmmuV3Node {
 546   /// An unique token used to identify this object
 547   CM_OBJECT_TOKEN   Token;
 548   /// Number of ID mappings
 549   UINT32            IdMappingCount;
 550   /// Reference token for the ID mapping array
 551   CM_OBJECT_TOKEN   IdMappingToken;
 552
 553   /// SMMU Base Address
 554   UINT64    BaseAddress;
 555   /// SMMU flags
 556   UINT32            Flags;
 557   /// VATOS address
 558   UINT64            VatosAddress;
 559   /// Model
 560   UINT32            Model;
 561   /// GSIV of the Event interrupt if SPI based
 562   UINT32            EventInterrupt;
 563   /// PRI Interrupt if SPI based
 564   UINT32            PriInterrupt;
 565   /// GERR interrupt if GSIV based
 566   UINT32            GerrInterrupt;
 567   /// Sync interrupt if GSIV based
 568   UINT32            SyncInterrupt;
 569
 570   /// Proximity domain flag
 571   UINT32            ProximityDomain;
 572   /// Index into the array of ID mapping
 573   UINT32            DeviceIdMappingIndex;
 574 } CM_ARM_SMMUV3_NODE;
 575
 576 /** A structure that describes the
 577     PMCG node for the Platform.
 578
 579     ID: EArmObjPmcg
 580 */
 581 typedef struct CmArmPmcgNode {
 582   /// An unique token used to identify this object
 583   CM_OBJECT_TOKEN   Token;
 584   /// Number of ID mappings
 585   UINT32            IdMappingCount;
 586   /// Reference token for the ID mapping array
 587   CM_OBJECT_TOKEN   IdMappingToken;
 588
 589   /// Base Address for performance monitor counter group
 590   UINT64            BaseAddress;
 591   /// GSIV for the Overflow interrupt
 592   UINT32            OverflowInterrupt;
 593   /// Page 1 Base address
 594   UINT64            Page1BaseAddress;
 595
 596   /// Reference token for the IORT node associated with this node
 597   CM_OBJECT_TOKEN   ReferenceToken;
 598 } CM_ARM_PMCG_NODE;
 599
 600 /** A structure that describes the
 601     ID Mappings for the Platform.
 602
 603     ID: EArmObjIdMappingArray
 604 */
 605 typedef struct CmArmIdMapping {
 606   /// Input base
 607   UINT32           InputBase;
 608   /// Number of input IDs
 609   UINT32           NumIds;
 610   /// Output Base
 611   UINT32           OutputBase;
 612   /// Reference token for the output node
 613   CM_OBJECT_TOKEN  OutputReferenceToken;
 614   /// Flags
 615   UINT32    Flags;
 616 } CM_ARM_ID_MAPPING;
 617
 618 /** A structure that describes the
 619     SMMU interrupts for the Platform.
 620
 621     ID: EArmObjSmmuInterruptArray
 622 */
 623 typedef struct CmArmSmmuInterrupt {
 624   /// Interrupt number
 625   UINT32    Interrupt;
 626
 627   /// Flags
 628   UINT32    Flags;
 629 } CM_ARM_SMMU_INTERRUPT;
 630
 631 #pragma pack()
 632
 633 #endif // ARM_NAMESPACE_OBJECTS_H_