DynamicTablesPkg/Include/ArmNameSpaceObjects.h

   1 /** @file
   2
   3   Copyright (c) 2017 - 2019, ARM Limited. All rights reserved.
   4
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7   @par Glossary:
   8     - Cm or CM   - Configuration Manager
   9     - Obj or OBJ - Object
  10     - Std or STD - Standard
  11 **/
  12
  13 #ifndef ARM_NAMESPACE_OBJECTS_H_
  14 #define ARM_NAMESPACE_OBJECTS_H_
  15
  16 #include <StandardNameSpaceObjects.h>
  17
  18 #pragma pack(1)
  19
  20 /** The EARM_OBJECT_ID enum describes the Object IDs
  21     in the ARM Namespace
  22 */
  23 typedef enum ArmObjectID {
  24   EArmObjReserved,                     ///<  0 - Reserved
  25   EArmObjBootArchInfo,                 ///<  1 - Boot Architecture Info
  26   EArmObjCpuInfo,                      ///<  2 - CPU Info
  27   EArmObjPowerManagementProfileInfo,   ///<  3 - Power Management Profile Info
  28   EArmObjGicCInfo,                     ///<  4 - GIC CPU Interface Info
  29   EArmObjGicDInfo,                     ///<  5 - GIC Distributor Info
  30   EArmObjGicMsiFrameInfo,              ///<  6 - GIC MSI Frame Info
  31   EArmObjGicRedistributorInfo,         ///<  7 - GIC Redistributor Info
  32   EArmObjGicItsInfo,                   ///<  8 - GIC ITS Info
  33   EArmObjSerialConsolePortInfo,        ///<  9 - Serial Console Port Info
  34   EArmObjSerialDebugPortInfo,          ///< 10 - Serial Debug Port Info
  35   EArmObjGenericTimerInfo,             ///< 11 - Generic Timer Info
  36   EArmObjPlatformGTBlockInfo,          ///< 12 - Platform GT Block Info
  37   EArmObjGTBlockTimerFrameInfo,        ///< 13 - Generic Timer Block Frame Info
  38   EArmObjPlatformGenericWatchdogInfo,  ///< 14 - Platform Generic Watchdog
  39   EArmObjPciConfigSpaceInfo,           ///< 15 - PCI Configuration Space Info
  40   EArmObjHypervisorVendorIdentity,     ///< 16 - Hypervisor Vendor Id
  41   EArmObjFixedFeatureFlags,            ///< 17 - Fixed feature flags for FADT
  42   EArmObjItsGroup,                     ///< 18 - ITS Group
  43   EArmObjNamedComponent,               ///< 19 - Named Component
  44   EArmObjRootComplex,                  ///< 20 - Root Complex
  45   EArmObjSmmuV1SmmuV2,                 ///< 21 - SMMUv1 or SMMUv2
  46   EArmObjSmmuV3,                       ///< 22 - SMMUv3
  47   EArmObjPmcg,                         ///< 23 - PMCG
  48   EArmObjGicItsIdentifierArray,        ///< 24 - GIC ITS Identifier Array
  49   EArmObjIdMappingArray,               ///< 25 - ID Mapping Array
  50   EArmObjSmmuInterruptArray,           ///< 26 - SMMU Interrupt Array
  51   EArmObjProcHierarchyInfo,            ///< 27 - Processor Hierarchy Info
  52   EArmObjCacheInfo,                    ///< 28 - Cache Info
  53   EArmObjProcNodeIdInfo,               ///< 29 - Processor Node ID Info
  54   EArmObjCmRef,                        ///< 30 - CM Object Reference
  55   EArmObjMemoryAffinityInfo,           ///< 31 - Memory Affinity Info
  56   EArmObjDeviceHandleAcpi,             ///< 32 - Device Handle Acpi
  57   EArmObjDeviceHandlePci,              ///< 33 - Device Handle Pci
  58   EArmObjGenericInitiatorAffinityInfo, ///< 34 - Generic Initiator Affinity
  59   EArmObjMax
  60 } EARM_OBJECT_ID;
  61
  62 /** A structure that describes the
  63     ARM Boot Architecture flags.
  64
  65     ID: EArmObjBootArchInfo
  66 */
  67 typedef struct CmArmBootArchInfo {
  68   /** This is the ARM_BOOT_ARCH flags field of the FADT Table
  69       described in the ACPI Table Specification.
  70   */
  71   UINT32  BootArchFlags;
  72 } CM_ARM_BOOT_ARCH_INFO;
  73
  74 typedef struct CmArmCpuInfo {
  75   // Reserved for use when SMBIOS tables are implemented
  76 } CM_ARM_CPU_INFO;
  77
  78 /** A structure that describes the
  79     Power Management Profile Information for the Platform.
  80
  81     ID: EArmObjPowerManagementProfileInfo
  82 */
  83 typedef struct CmArmPowerManagementProfileInfo {
  84   /** This is the Preferred_PM_Profile field of the FADT Table
  85       described in the ACPI Specification
  86   */
  87   UINT8  PowerManagementProfile;
  88 } CM_ARM_POWER_MANAGEMENT_PROFILE_INFO;
  89
  90 /** A structure that describes the
  91     GIC CPU Interface for the Platform.
  92
  93     ID: EArmObjGicCInfo
  94 */
  95 typedef struct CmArmGicCInfo {
  96   /// The GIC CPU Interface number.
  97   UINT32  CPUInterfaceNumber;
  98
  99   /** The ACPI Processor UID. This must match the
 100       _UID of the CPU Device object information described
 101       in the DSDT/SSDT for the CPU.
 102   */
 103   UINT32  AcpiProcessorUid;
 104
 105   /** The flags field as described by the GICC structure
 106       in the ACPI Specification.
 107   */
 108   UINT32  Flags;
 109
 110   /** The parking protocol version field as described by
 111     the GICC structure in the ACPI Specification.
 112   */
 113   UINT32  ParkingProtocolVersion;
 114
 115   /** The Performance Interrupt field as described by
 116       the GICC structure in the ACPI Specification.
 117   */
 118   UINT32  PerformanceInterruptGsiv;
 119
 120   /** The CPU Parked address field as described by
 121       the GICC structure in the ACPI Specification.
 122   */
 123   UINT64  ParkedAddress;
 124
 125   /** The base address for the GIC CPU Interface
 126       as described by the GICC structure in the
 127       ACPI Specification.
 128   */
 129   UINT64  PhysicalBaseAddress;
 130
 131   /** The base address for GICV interface
 132       as described by the GICC structure in the
 133       ACPI Specification.
 134   */
 135   UINT64  GICV;
 136
 137   /** The base address for GICH interface
 138       as described by the GICC structure in the
 139       ACPI Specification.
 140   */
 141   UINT64  GICH;
 142
 143   /** The GICV maintenance interrupt
 144       as described by the GICC structure in the
 145       ACPI Specification.
 146   */
 147   UINT32  VGICMaintenanceInterrupt;
 148
 149   /** The base address for GICR interface
 150       as described by the GICC structure in the
 151       ACPI Specification.
 152   */
 153   UINT64  GICRBaseAddress;
 154
 155   /** The MPIDR for the CPU
 156       as described by the GICC structure in the
 157       ACPI Specification.
 158   */
 159   UINT64  MPIDR;
 160
 161   /** The Processor Power Efficiency class
 162       as described by the GICC structure in the
 163       ACPI Specification.
 164   */
 165   UINT8   ProcessorPowerEfficiencyClass;
 166
 167   /** Statistical Profiling Extension buffer overflow GSIV. Zero if
 168       unsupported by this processor. This field was introduced in
 169       ACPI 6.3 (MADT revision 5) and is therefore ignored when
 170       generating MADT revision 4 or lower.
 171   */
 172   UINT16  SpeOverflowInterrupt;
 173
 174   /** The proximity domain to which the logical processor belongs.
 175       This field is used to populate the GICC affinity structure
 176       in the SRAT table.
 177   */
 178   UINT32  ProximityDomain;
 179
 180   /** The clock domain to which the logical processor belongs.
 181       This field is used to populate the GICC affinity structure
 182       in the SRAT table.
 183   */
 184   UINT32  ClockDomain;
 185
 186   /** The GICC Affinity flags field as described by the GICC Affinity structure
 187       in the SRAT table.
 188   */
 189   UINT32  AffinityFlags;
 190 } CM_ARM_GICC_INFO;
 191
 192 /** A structure that describes the
 193     GIC Distributor information for the Platform.
 194
 195     ID: EArmObjGicDInfo
 196 */
 197 typedef struct CmArmGicDInfo {
 198   /// The Physical Base address for the GIC Distributor.
 199   UINT64  PhysicalBaseAddress;
 200
 201   /** The global system interrupt
 202       number where this GIC Distributor's
 203       interrupt inputs start.
 204   */
 205   UINT32  SystemVectorBase;
 206
 207   /** The GIC version as described
 208       by the GICD structure in the
 209       ACPI Specification.
 210   */
 211   UINT8   GicVersion;
 212 } CM_ARM_GICD_INFO;
 213
 214 /** A structure that describes the
 215     GIC MSI Frame information for the Platform.
 216
 217     ID: EArmObjGicMsiFrameInfo
 218 */
 219 typedef struct CmArmGicMsiFrameInfo {
 220   /// The GIC MSI Frame ID
 221   UINT32  GicMsiFrameId;
 222
 223   /// The Physical base address for the MSI Frame
 224   UINT64  PhysicalBaseAddress;
 225
 226   /** The GIC MSI Frame flags
 227       as described by the GIC MSI frame
 228       structure in the ACPI Specification.
 229   */
 230   UINT32  Flags;
 231
 232   /// SPI Count used by this frame
 233   UINT16  SPICount;
 234
 235   /// SPI Base used by this frame
 236   UINT16  SPIBase;
 237 } CM_ARM_GIC_MSI_FRAME_INFO;
 238
 239 /** A structure that describes the
 240     GIC Redistributor information for the Platform.
 241
 242     ID: EArmObjGicRedistributorInfo
 243 */
 244 typedef struct CmArmGicRedistInfo {
 245   /** The physical address of a page range
 246       containing all GIC Redistributors.
 247   */
 248   UINT64  DiscoveryRangeBaseAddress;
 249
 250   /// Length of the GIC Redistributor Discovery page range
 251   UINT32  DiscoveryRangeLength;
 252 } CM_ARM_GIC_REDIST_INFO;
 253
 254 /** A structure that describes the
 255     GIC Interrupt Translation Service information for the Platform.
 256
 257     ID: EArmObjGicItsInfo
 258 */
 259 typedef struct CmArmGicItsInfo {
 260   /// The GIC ITS ID
 261   UINT32  GicItsId;
 262
 263   /// The physical address for the Interrupt Translation Service
 264   UINT64  PhysicalBaseAddress;
 265
 266   /** The proximity domain to which the logical processor belongs.
 267       This field is used to populate the GIC ITS affinity structure
 268       in the SRAT table.
 269   */
 270   UINT32  ProximityDomain;
 271 } CM_ARM_GIC_ITS_INFO;
 272
 273 /** A structure that describes the
 274     Serial Port information for the Platform.
 275
 276     ID: EArmObjSerialConsolePortInfo or
 277         EArmObjSerialDebugPortInfo
 278 */
 279 typedef struct CmArmSerialPortInfo {
 280   /// The physical base address for the serial port
 281   UINT64  BaseAddress;
 282
 283   /// The serial port interrupt
 284   UINT32  Interrupt;
 285
 286   /// The serial port baud rate
 287   UINT64  BaudRate;
 288
 289   /// The serial port clock
 290   UINT32  Clock;
 291
 292   /// Serial Port subtype
 293   UINT16  PortSubtype;
 294 } CM_ARM_SERIAL_PORT_INFO;
 295
 296 /** A structure that describes the
 297     Generic Timer information for the Platform.
 298
 299     ID: EArmObjGenericTimerInfo
 300 */
 301 typedef struct CmArmGenericTimerInfo {
 302   /// The physical base address for the counter control frame
 303   UINT64  CounterControlBaseAddress;
 304
 305   /// The physical base address for the counter read frame
 306   UINT64  CounterReadBaseAddress;
 307
 308   /// The secure PL1 timer interrupt
 309   UINT32  SecurePL1TimerGSIV;
 310
 311   /// The secure PL1 timer flags
 312   UINT32  SecurePL1TimerFlags;
 313
 314   /// The non-secure PL1 timer interrupt
 315   UINT32  NonSecurePL1TimerGSIV;
 316
 317   /// The non-secure PL1 timer flags
 318   UINT32  NonSecurePL1TimerFlags;
 319
 320   /// The virtual timer interrupt
 321   UINT32  VirtualTimerGSIV;
 322
 323   /// The virtual timer flags
 324   UINT32  VirtualTimerFlags;
 325
 326   /// The non-secure PL2 timer interrupt
 327   UINT32  NonSecurePL2TimerGSIV;
 328
 329   /// The non-secure PL2 timer flags
 330   UINT32  NonSecurePL2TimerFlags;
 331
 332   /// GSIV for the virtual EL2 timer
 333   UINT32  VirtualPL2TimerGSIV;
 334
 335   /// Flags for the virtual EL2 timer
 336   UINT32  VirtualPL2TimerFlags;
 337 } CM_ARM_GENERIC_TIMER_INFO;
 338
 339 /** A structure that describes the
 340     Platform Generic Block Timer Frame information for the Platform.
 341
 342     ID: EArmObjGTBlockTimerFrameInfo
 343 */
 344 typedef struct CmArmGTBlockTimerFrameInfo {
 345   /// The Generic Timer frame number
 346   UINT8   FrameNumber;
 347
 348   /// The physical base address for the CntBase block
 349   UINT64  PhysicalAddressCntBase;
 350
 351   /// The physical base address for the CntEL0Base block
 352   UINT64  PhysicalAddressCntEL0Base;
 353
 354   /// The physical timer interrupt
 355   UINT32  PhysicalTimerGSIV;
 356
 357   /** The physical timer flags as described by the GT Block
 358       Timer frame Structure in the ACPI Specification.
 359   */
 360   UINT32  PhysicalTimerFlags;
 361
 362   /// The virtual timer interrupt
 363   UINT32  VirtualTimerGSIV;
 364
 365   /** The virtual timer flags as described by the GT Block
 366       Timer frame Structure in the ACPI Specification.
 367   */
 368   UINT32  VirtualTimerFlags;
 369
 370   /** The common timer flags as described by the GT Block
 371       Timer frame Structure in the ACPI Specification.
 372   */
 373   UINT32  CommonFlags;
 374 } CM_ARM_GTBLOCK_TIMER_FRAME_INFO;
 375
 376 /** A structure that describes the
 377     Platform Generic Block Timer information for the Platform.
 378
 379     ID: EArmObjPlatformGTBlockInfo
 380 */
 381 typedef struct CmArmGTBlockInfo {
 382   /// The physical base address for the GT Block Timer structure
 383   UINT64            GTBlockPhysicalAddress;
 384
 385   /// The number of timer frames implemented in the GT Block
 386   UINT32            GTBlockTimerFrameCount;
 387
 388   /// Reference token for the GT Block timer frame list
 389   CM_OBJECT_TOKEN   GTBlockTimerFrameToken;
 390 } CM_ARM_GTBLOCK_INFO;
 391
 392 /** A structure that describes the
 393     SBSA Generic Watchdog information for the Platform.
 394
 395     ID: EArmObjPlatformGenericWatchdogInfo
 396 */
 397 typedef struct CmArmGenericWatchdogInfo {
 398   /// The physical base address of the SBSA Watchdog control frame
 399   UINT64  ControlFrameAddress;
 400
 401   /// The physical base address of the SBSA Watchdog refresh frame
 402   UINT64  RefreshFrameAddress;
 403
 404   /// The watchdog interrupt
 405   UINT32  TimerGSIV;
 406
 407   /** The flags for the watchdog as described by the SBSA watchdog
 408       structure in the ACPI specification.
 409   */
 410   UINT32  Flags;
 411 } CM_ARM_GENERIC_WATCHDOG_INFO;
 412
 413 /** A structure that describes the
 414     PCI Configuration Space information for the Platform.
 415
 416     ID: EArmObjPciConfigSpaceInfo
 417 */
 418 typedef struct CmArmPciConfigSpaceInfo {
 419   /// The physical base address for the PCI segment
 420   UINT64  BaseAddress;
 421
 422   /// The PCI segment group number
 423   UINT16  PciSegmentGroupNumber;
 424
 425   /// The start bus number
 426   UINT8   StartBusNumber;
 427
 428   /// The end bus number
 429   UINT8   EndBusNumber;
 430 } CM_ARM_PCI_CONFIG_SPACE_INFO;
 431
 432 /** A structure that describes the
 433     Hypervisor Vendor ID information for the Platform.
 434
 435     ID: EArmObjHypervisorVendorIdentity
 436 */
 437 typedef struct CmArmHypervisorVendorId {
 438   /// The hypervisor Vendor ID
 439   UINT64  HypervisorVendorId;
 440 } CM_ARM_HYPERVISOR_VENDOR_ID;
 441
 442 /** A structure that describes the
 443     Fixed feature flags for the Platform.
 444
 445     ID: EArmObjFixedFeatureFlags
 446 */
 447 typedef struct CmArmFixedFeatureFlags {
 448   /// The Fixed feature flags
 449   UINT32  Flags;
 450 } CM_ARM_FIXED_FEATURE_FLAGS;
 451
 452 /** A structure that describes the
 453     ITS Group node for the Platform.
 454
 455     ID: EArmObjItsGroup
 456 */
 457 typedef struct CmArmItsGroupNode {
 458   /// An unique token used to identify this object
 459   CM_OBJECT_TOKEN   Token;
 460   /// The number of ITS identifiers in the ITS node
 461   UINT32            ItsIdCount;
 462   /// Reference token for the ITS identifier array
 463   CM_OBJECT_TOKEN   ItsIdToken;
 464 } CM_ARM_ITS_GROUP_NODE;
 465
 466 /** A structure that describes the
 467     GIC ITS Identifiers for an ITS Group node.
 468
 469     ID: EArmObjGicItsIdentifierArray
 470 */
 471 typedef struct CmArmGicItsIdentifier {
 472   /// The ITS Identifier
 473   UINT32  ItsId;
 474 } CM_ARM_ITS_IDENTIFIER;
 475
 476 /** A structure that describes the
 477     Named component node for the Platform.
 478
 479     ID: EArmObjNamedComponent
 480 */
 481 typedef struct CmArmNamedComponentNode {
 482   /// An unique token used to identify this object
 483   CM_OBJECT_TOKEN   Token;
 484   /// Number of ID mappings
 485   UINT32            IdMappingCount;
 486   /// Reference token for the ID mapping array
 487   CM_OBJECT_TOKEN   IdMappingToken;
 488
 489   /// Flags for the named component
 490   UINT32            Flags;
 491
 492   /// Memory access properties : Cache coherent attributes
 493   UINT32            CacheCoherent;
 494   /// Memory access properties : Allocation hints
 495   UINT8             AllocationHints;
 496   /// Memory access properties : Memory access flags
 497   UINT8             MemoryAccessFlags;
 498
 499   /// Memory access properties : Address size limit
 500   UINT8             AddressSizeLimit;
 501   /** ASCII Null terminated string with the full path to
 502       the entry in the namespace for this object.
 503   */
 504   CHAR8*            ObjectName;
 505 } CM_ARM_NAMED_COMPONENT_NODE;
 506
 507 /** A structure that describes the
 508     Root complex node for the Platform.
 509
 510     ID: EArmObjRootComplex
 511 */
 512 typedef struct CmArmRootComplexNode {
 513   /// An unique token used to identify this object
 514   CM_OBJECT_TOKEN   Token;
 515   /// Number of ID mappings
 516   UINT32            IdMappingCount;
 517   /// Reference token for the ID mapping array
 518   CM_OBJECT_TOKEN   IdMappingToken;
 519
 520   /// Memory access properties : Cache coherent attributes
 521   UINT32            CacheCoherent;
 522   /// Memory access properties : Allocation hints
 523   UINT8             AllocationHints;
 524   /// Memory access properties : Memory access flags
 525   UINT8             MemoryAccessFlags;
 526
 527   /// ATS attributes
 528   UINT32            AtsAttribute;
 529   /// PCI segment number
 530   UINT32            PciSegmentNumber;
 531   /// Memory address size limit
 532   UINT8             MemoryAddressSize;
 533 } CM_ARM_ROOT_COMPLEX_NODE;
 534
 535 /** A structure that describes the
 536     SMMUv1 or SMMUv2 node for the Platform.
 537
 538     ID: EArmObjSmmuV1SmmuV2
 539 */
 540 typedef struct CmArmSmmuV1SmmuV2Node {
 541   /// An unique token used to identify this object
 542   CM_OBJECT_TOKEN   Token;
 543   /// Number of ID mappings
 544   UINT32            IdMappingCount;
 545   /// Reference token for the ID mapping array
 546   CM_OBJECT_TOKEN   IdMappingToken;
 547
 548   /// SMMU Base Address
 549   UINT64            BaseAddress;
 550   /// Length of the memory range covered by the SMMU
 551   UINT64            Span;
 552   /// SMMU Model
 553   UINT32            Model;
 554   /// SMMU flags
 555   UINT32            Flags;
 556
 557   /// Number of context interrupts
 558   UINT32            ContextInterruptCount;
 559   /// Reference token for the context interrupt array
 560   CM_OBJECT_TOKEN   ContextInterruptToken;
 561
 562   /// Number of PMU interrupts
 563   UINT32            PmuInterruptCount;
 564   /// Reference token for the PMU interrupt array
 565   CM_OBJECT_TOKEN   PmuInterruptToken;
 566
 567   /// GSIV of the SMMU_NSgIrpt interrupt
 568   UINT32            SMMU_NSgIrpt;
 569   /// SMMU_NSgIrpt interrupt flags
 570   UINT32            SMMU_NSgIrptFlags;
 571   /// GSIV of the SMMU_NSgCfgIrpt interrupt
 572   UINT32            SMMU_NSgCfgIrpt;
 573   /// SMMU_NSgCfgIrpt interrupt flags
 574   UINT32            SMMU_NSgCfgIrptFlags;
 575 } CM_ARM_SMMUV1_SMMUV2_NODE;
 576
 577 /** A structure that describes the
 578     SMMUv3 node for the Platform.
 579
 580     ID: EArmObjSmmuV3
 581 */
 582 typedef struct CmArmSmmuV3Node {
 583   /// An unique token used to identify this object
 584   CM_OBJECT_TOKEN   Token;
 585   /// Number of ID mappings
 586   UINT32            IdMappingCount;
 587   /// Reference token for the ID mapping array
 588   CM_OBJECT_TOKEN   IdMappingToken;
 589
 590   /// SMMU Base Address
 591   UINT64    BaseAddress;
 592   /// SMMU flags
 593   UINT32            Flags;
 594   /// VATOS address
 595   UINT64            VatosAddress;
 596   /// Model
 597   UINT32            Model;
 598   /// GSIV of the Event interrupt if SPI based
 599   UINT32            EventInterrupt;
 600   /// PRI Interrupt if SPI based
 601   UINT32            PriInterrupt;
 602   /// GERR interrupt if GSIV based
 603   UINT32            GerrInterrupt;
 604   /// Sync interrupt if GSIV based
 605   UINT32            SyncInterrupt;
 606
 607   /// Proximity domain flag
 608   UINT32            ProximityDomain;
 609   /// Index into the array of ID mapping
 610   UINT32            DeviceIdMappingIndex;
 611 } CM_ARM_SMMUV3_NODE;
 612
 613 /** A structure that describes the
 614     PMCG node for the Platform.
 615
 616     ID: EArmObjPmcg
 617 */
 618 typedef struct CmArmPmcgNode {
 619   /// An unique token used to identify this object
 620   CM_OBJECT_TOKEN   Token;
 621   /// Number of ID mappings
 622   UINT32            IdMappingCount;
 623   /// Reference token for the ID mapping array
 624   CM_OBJECT_TOKEN   IdMappingToken;
 625
 626   /// Base Address for performance monitor counter group
 627   UINT64            BaseAddress;
 628   /// GSIV for the Overflow interrupt
 629   UINT32            OverflowInterrupt;
 630   /// Page 1 Base address
 631   UINT64            Page1BaseAddress;
 632
 633   /// Reference token for the IORT node associated with this node
 634   CM_OBJECT_TOKEN   ReferenceToken;
 635 } CM_ARM_PMCG_NODE;
 636
 637 /** A structure that describes the
 638     ID Mappings for the Platform.
 639
 640     ID: EArmObjIdMappingArray
 641 */
 642 typedef struct CmArmIdMapping {
 643   /// Input base
 644   UINT32           InputBase;
 645   /// Number of input IDs
 646   UINT32           NumIds;
 647   /// Output Base
 648   UINT32           OutputBase;
 649   /// Reference token for the output node
 650   CM_OBJECT_TOKEN  OutputReferenceToken;
 651   /// Flags
 652   UINT32    Flags;
 653 } CM_ARM_ID_MAPPING;
 654
 655 /** A structure that describes the
 656     SMMU interrupts for the Platform.
 657
 658     ID: EArmObjSmmuInterruptArray
 659 */
 660 typedef struct CmArmSmmuInterrupt {
 661   /// Interrupt number
 662   UINT32    Interrupt;
 663
 664   /// Flags
 665   UINT32    Flags;
 666 } CM_ARM_SMMU_INTERRUPT;
 667
 668 /** A structure that describes the Processor Hierarchy Node (Type 0) in PPTT
 669
 670     ID: EArmObjProcHierarchyInfo
 671 */
 672 typedef struct CmArmProcHierarchyInfo {
 673   /// A unique token used to identify this object
 674   CM_OBJECT_TOKEN   Token;
 675   /// Processor structure flags (ACPI 6.3 - January 2019, PPTT, Table 5-155)
 676   UINT32            Flags;
 677   /// Token for the parent CM_ARM_PROC_HIERARCHY_INFO object in the processor
 678   /// topology. A value of CM_NULL_TOKEN means this node has no parent.
 679   CM_OBJECT_TOKEN   ParentToken;
 680   /// Token of the associated CM_ARM_GICC_INFO object which has the
 681   /// corresponding ACPI Processor ID. A value of CM_NULL_TOKEN means this
 682   /// node represents a group of associated processors and it does not have an
 683   /// associated GIC CPU interface.
 684   CM_OBJECT_TOKEN   GicCToken;
 685   /// Number of resources private to this Node
 686   UINT32            NoOfPrivateResources;
 687   /// Token of the array which contains references to the resources private to
 688   /// this CM_ARM_PROC_HIERARCHY_INFO instance. This field is ignored if
 689   /// the NoOfPrivateResources is 0, in which case it is recomended to set
 690   /// this field to CM_NULL_TOKEN.
 691   CM_OBJECT_TOKEN   PrivateResourcesArrayToken;
 692 } CM_ARM_PROC_HIERARCHY_INFO;
 693
 694 /** A structure that describes the Cache Type Structure (Type 1) in PPTT
 695
 696     ID: EArmObjCacheInfo
 697 */
 698 typedef struct CmArmCacheInfo {
 699   /// A unique token used to identify this object
 700   CM_OBJECT_TOKEN   Token;
 701   /// Reference token for the next level of cache that is private to the same
 702   /// CM_ARM_PROC_HIERARCHY_INFO instance. A value of CM_NULL_TOKEN means this
 703   /// entry represents the last cache level appropriate to the processor
 704   /// hierarchy node structures using this entry.
 705   CM_OBJECT_TOKEN   NextLevelOfCacheToken;
 706   /// Size of the cache in bytes
 707   UINT32            Size;
 708   /// Number of sets in the cache
 709   UINT32            NumberOfSets;
 710   /// Integer number of ways. The maximum associativity supported by
 711   /// ACPI Cache type structure is limited to MAX_UINT8. However,
 712   /// the maximum number of ways supported by the architecture is
 713   /// PPTT_ARM_CCIDX_CACHE_ASSOCIATIVITY_MAX. Therfore this field
 714   /// is 32-bit wide.
 715   UINT32            Associativity;
 716   /// Cache attributes (ACPI 6.3 - January 2019, PPTT, Table 5-156)
 717   UINT8             Attributes;
 718   /// Line size in bytes
 719   UINT16            LineSize;
 720 } CM_ARM_CACHE_INFO;
 721
 722 /** A structure that describes the ID Structure (Type 2) in PPTT
 723
 724     ID: EArmObjProcNodeIdInfo
 725 */
 726 typedef struct CmArmProcNodeIdInfo {
 727   /// A unique token used to identify this object
 728   CM_OBJECT_TOKEN   Token;
 729   // Vendor ID (as described in ACPI ID registry)
 730   UINT32            VendorId;
 731   /// First level unique node ID
 732   UINT64            Level1Id;
 733   /// Second level unique node ID
 734   UINT64            Level2Id;
 735   /// Major revision of the node
 736   UINT16            MajorRev;
 737   /// Minor revision of the node
 738   UINT16            MinorRev;
 739   /// Spin revision of the node
 740   UINT16            SpinRev;
 741 } CM_ARM_PROC_NODE_ID_INFO;
 742
 743 /** A structure that describes a reference to another Configuration Manager
 744     object.
 745
 746     This is useful for creating an array of reference tokens. The framework
 747     can then query the configuration manager for these arrays using the
 748     object ID EArmObjCmRef.
 749
 750     This can be used is to represent one-to-many relationships between objects.
 751
 752     ID: EArmObjCmRef
 753 */
 754 typedef struct CmArmObjRef {
 755   /// Token of the CM object being referenced
 756   CM_OBJECT_TOKEN   ReferenceToken;
 757 } CM_ARM_OBJ_REF;
 758
 759 /** A structure that describes the Memory Affinity Structure (Type 1) in SRAT
 760
 761     ID: EArmObjMemoryAffinityInfo
 762 */
 763 typedef struct CmArmMemoryAffinityInfo {
 764   /// The proximity domain to which the "range of memory" belongs.
 765   UINT32            ProximityDomain;
 766
 767   /// Base Address
 768   UINT64            BaseAddress;
 769
 770   /// Length
 771   UINT64            Length;
 772
 773   /// Flags
 774   UINT32            Flags;
 775 } CM_ARM_MEMORY_AFFINITY_INFO;
 776
 777 /** A structure that describes the ACPI Device Handle (Type 0) in the
 778     Generic Initiator Affinity structure in SRAT
 779
 780     ID: EArmObjDeviceHandleAcpi
 781 */
 782 typedef struct CmArmDeviceHandleAcpi {
 783   /// Hardware ID
 784   UINT64  Hid;
 785
 786   /// Unique Id
 787   UINT32  Uid;
 788 } CM_ARM_DEVICE_HANDLE_ACPI;
 789
 790 /** A structure that describes the PCI Device Handle (Type 1) in the
 791     Generic Initiator Affinity structure in SRAT
 792
 793     ID: EArmObjDeviceHandlePci
 794 */
 795 typedef struct CmArmDeviceHandlePci {
 796   /// PCI Segment Number
 797   UINT16  SegmentNumber;
 798
 799   /// PCI Bus Number - Max 256 busses (Bits 15:8 of BDF)
 800   UINT8  BusNumber;
 801
 802   /// PCI Device Mumber - Max 32 devices (Bits 7:3 of BDF)
 803   UINT8   DeviceNumber;
 804
 805   /// PCI Function Number - Max 8 functions (Bits 2:0 of BDF)
 806   UINT8   FunctionNumber;
 807 } CM_ARM_DEVICE_HANDLE_PCI;
 808
 809 /** A structure that describes the Generic Initiator Affinity structure in SRAT
 810
 811     ID: EArmObjGenericInitiatorAffinityInfo
 812 */
 813 typedef struct CmArmGenericInitiatorAffinityInfo {
 814   /// The proximity domain to which the generic initiator belongs.
 815   UINT32            ProximityDomain;
 816
 817   /// Flags
 818   UINT32            Flags;
 819
 820   /// Device Handle Type
 821   UINT8             DeviceHandleType;
 822
 823   /// Reference Token for the Device Handle
 824   CM_OBJECT_TOKEN   DeviceHandleToken;
 825 } CM_ARM_GENERIC_INITIATOR_AFFINITY_INFO;
 826
 827 #pragma pack()
 828
 829 #endif // ARM_NAMESPACE_OBJECTS_H_