3 Copyright (c) 2017 - 2019, ARM Limited. All rights reserved.
5 SPDX-License-Identifier: BSD-2-Clause-Patent
8 - Cm or CM - Configuration Manager
10 - Std or STD - Standard
13 #ifndef ARM_NAMESPACE_OBJECTS_H_
14 #define ARM_NAMESPACE_OBJECTS_H_
16 #include <StandardNameSpaceObjects.h>
20 /** The EARM_OBJECT_ID enum describes the Object IDs
23 typedef enum ArmObjectID
{
24 EArmObjReserved
, ///< 0 - Reserved
25 EArmObjBootArchInfo
, ///< 1 - Boot Architecture Info
26 EArmObjCpuInfo
, ///< 2 - CPU Info
27 EArmObjPowerManagementProfileInfo
, ///< 3 - Power Management Profile Info
28 EArmObjGicCInfo
, ///< 4 - GIC CPU Interface Info
29 EArmObjGicDInfo
, ///< 5 - GIC Distributor Info
30 EArmObjGicMsiFrameInfo
, ///< 6 - GIC MSI Frame Info
31 EArmObjGicRedistributorInfo
, ///< 7 - GIC Redistributor Info
32 EArmObjGicItsInfo
, ///< 8 - GIC ITS Info
33 EArmObjSerialConsolePortInfo
, ///< 9 - Serial Console Port Info
34 EArmObjSerialDebugPortInfo
, ///< 10 - Serial Debug Port Info
35 EArmObjGenericTimerInfo
, ///< 11 - Generic Timer Info
36 EArmObjPlatformGTBlockInfo
, ///< 12 - Platform GT Block Info
37 EArmObjGTBlockTimerFrameInfo
, ///< 13 - Generic Timer Block Frame Info
38 EArmObjPlatformGenericWatchdogInfo
, ///< 14 - Platform Generic Watchdog
39 EArmObjPciConfigSpaceInfo
, ///< 15 - PCI Configuration Space Info
40 EArmObjHypervisorVendorIdentity
, ///< 16 - Hypervisor Vendor Id
41 EArmObjFixedFeatureFlags
, ///< 17 - Fixed feature flags for FADT
42 EArmObjItsGroup
, ///< 18 - ITS Group
43 EArmObjNamedComponent
, ///< 19 - Named Component
44 EArmObjRootComplex
, ///< 20 - Root Complex
45 EArmObjSmmuV1SmmuV2
, ///< 21 - SMMUv1 or SMMUv2
46 EArmObjSmmuV3
, ///< 22 - SMMUv3
47 EArmObjPmcg
, ///< 23 - PMCG
48 EArmObjGicItsIdentifierArray
, ///< 24 - GIC ITS Identifier Array
49 EArmObjIdMappingArray
, ///< 25 - ID Mapping Array
50 EArmObjSmmuInterruptArray
, ///< 26 - SMMU Interrupt Array
54 /** A structure that describes the
55 ARM Boot Architecture flags.
57 ID: EArmObjBootArchInfo
59 typedef struct CmArmBootArchInfo
{
60 /** This is the ARM_BOOT_ARCH flags field of the FADT Table
61 described in the ACPI Table Specification.
64 } CM_ARM_BOOT_ARCH_INFO
;
66 typedef struct CmArmCpuInfo
{
67 // Reserved for use when SMBIOS tables are implemented
70 /** A structure that describes the
71 Power Management Profile Information for the Platform.
73 ID: EArmObjPowerManagementProfileInfo
75 typedef struct CmArmPowerManagementProfileInfo
{
76 /** This is the Preferred_PM_Profile field of the FADT Table
77 described in the ACPI Specification
79 UINT8 PowerManagementProfile
;
80 } CM_ARM_POWER_MANAGEMENT_PROFILE_INFO
;
82 /** A structure that describes the
83 GIC CPU Interface for the Platform.
87 typedef struct CmArmGicCInfo
{
88 /// The GIC CPU Interface number.
89 UINT32 CPUInterfaceNumber
;
91 /** The ACPI Processor UID. This must match the
92 _UID of the CPU Device object information described
93 in the DSDT/SSDT for the CPU.
95 UINT32 AcpiProcessorUid
;
97 /** The flags field as described by the GICC structure
98 in the ACPI Specification.
102 /** The parking protocol version field as described by
103 the GICC structure in the ACPI Specification.
105 UINT32 ParkingProtocolVersion
;
107 /** The Performance Interrupt field as described by
108 the GICC structure in the ACPI Specification.
110 UINT32 PerformanceInterruptGsiv
;
112 /** The CPU Parked address field as described by
113 the GICC structure in the ACPI Specification.
115 UINT64 ParkedAddress
;
117 /** The base address for the GIC CPU Interface
118 as described by the GICC structure in the
121 UINT64 PhysicalBaseAddress
;
123 /** The base address for GICV interface
124 as described by the GICC structure in the
129 /** The base address for GICH interface
130 as described by the GICC structure in the
135 /** The GICV maintenance interrupt
136 as described by the GICC structure in the
139 UINT32 VGICMaintenanceInterrupt
;
141 /** The base address for GICR interface
142 as described by the GICC structure in the
145 UINT64 GICRBaseAddress
;
147 /** The MPIDR for the CPU
148 as described by the GICC structure in the
153 /** The Processor Power Efficiency class
154 as described by the GICC structure in the
157 UINT8 ProcessorPowerEfficiencyClass
;
159 /** Statistical Profiling Extension buffer overflow GSIV. Zero if
160 unsupported by this processor. This field was introduced in
161 ACPI 6.3 (MADT revision 5) and is therefore ignored when
162 generating MADT revision 4 or lower.
164 UINT16 SpeOverflowInterrupt
;
167 /** A structure that describes the
168 GIC Distributor information for the Platform.
172 typedef struct CmArmGicDInfo
{
173 /// The Physical Base address for the GIC Distributor.
174 UINT64 PhysicalBaseAddress
;
176 /** The global system interrupt
177 number where this GIC Distributor's
178 interrupt inputs start.
180 UINT32 SystemVectorBase
;
182 /** The GIC version as described
183 by the GICD structure in the
189 /** A structure that describes the
190 GIC MSI Frame information for the Platform.
192 ID: EArmObjGicMsiFrameInfo
194 typedef struct CmArmGicMsiFrameInfo
{
195 /// The GIC MSI Frame ID
196 UINT32 GicMsiFrameId
;
198 /// The Physical base address for the MSI Frame
199 UINT64 PhysicalBaseAddress
;
201 /** The GIC MSI Frame flags
202 as described by the GIC MSI frame
203 structure in the ACPI Specification.
207 /// SPI Count used by this frame
210 /// SPI Base used by this frame
212 } CM_ARM_GIC_MSI_FRAME_INFO
;
214 /** A structure that describes the
215 GIC Redistributor information for the Platform.
217 ID: EArmObjGicRedistributorInfo
219 typedef struct CmArmGicRedistInfo
{
220 /** The physical address of a page range
221 containing all GIC Redistributors.
223 UINT64 DiscoveryRangeBaseAddress
;
225 /// Length of the GIC Redistributor Discovery page range
226 UINT32 DiscoveryRangeLength
;
227 } CM_ARM_GIC_REDIST_INFO
;
229 /** A structure that describes the
230 GIC Interrupt Translation Service information for the Platform.
232 ID: EArmObjGicItsInfo
234 typedef struct CmArmGicItsInfo
{
238 /// The physical address for the Interrupt Translation Service
239 UINT64 PhysicalBaseAddress
;
240 } CM_ARM_GIC_ITS_INFO
;
242 /** A structure that describes the
243 Serial Port information for the Platform.
245 ID: EArmObjSerialConsolePortInfo or
246 EArmObjSerialDebugPortInfo
248 typedef struct CmArmSerialPortInfo
{
249 /// The physical base address for the serial port
252 /// The serial port interrupt
255 /// The serial port baud rate
258 /// The serial port clock
261 /// Serial Port subtype
263 } CM_ARM_SERIAL_PORT_INFO
;
265 /** A structure that describes the
266 Generic Timer information for the Platform.
268 ID: EArmObjGenericTimerInfo
270 typedef struct CmArmGenericTimerInfo
{
271 /// The physical base address for the counter control frame
272 UINT64 CounterControlBaseAddress
;
274 /// The physical base address for the counter read frame
275 UINT64 CounterReadBaseAddress
;
277 /// The secure PL1 timer interrupt
278 UINT32 SecurePL1TimerGSIV
;
280 /// The secure PL1 timer flags
281 UINT32 SecurePL1TimerFlags
;
283 /// The non-secure PL1 timer interrupt
284 UINT32 NonSecurePL1TimerGSIV
;
286 /// The non-secure PL1 timer flags
287 UINT32 NonSecurePL1TimerFlags
;
289 /// The virtual timer interrupt
290 UINT32 VirtualTimerGSIV
;
292 /// The virtual timer flags
293 UINT32 VirtualTimerFlags
;
295 /// The non-secure PL2 timer interrupt
296 UINT32 NonSecurePL2TimerGSIV
;
298 /// The non-secure PL2 timer flags
299 UINT32 NonSecurePL2TimerFlags
;
300 } CM_ARM_GENERIC_TIMER_INFO
;
302 /** A structure that describes the
303 Platform Generic Block Timer Frame information for the Platform.
305 ID: EArmObjGTBlockTimerFrameInfo
307 typedef struct CmArmGTBlockTimerFrameInfo
{
308 /// The Generic Timer frame number
311 /// The physical base address for the CntBase block
312 UINT64 PhysicalAddressCntBase
;
314 /// The physical base address for the CntEL0Base block
315 UINT64 PhysicalAddressCntEL0Base
;
317 /// The physical timer interrupt
318 UINT32 PhysicalTimerGSIV
;
320 /** The physical timer flags as described by the GT Block
321 Timer frame Structure in the ACPI Specification.
323 UINT32 PhysicalTimerFlags
;
325 /// The virtual timer interrupt
326 UINT32 VirtualTimerGSIV
;
328 /** The virtual timer flags as described by the GT Block
329 Timer frame Structure in the ACPI Specification.
331 UINT32 VirtualTimerFlags
;
333 /** The common timer flags as described by the GT Block
334 Timer frame Structure in the ACPI Specification.
337 } CM_ARM_GTBLOCK_TIMER_FRAME_INFO
;
339 /** A structure that describes the
340 Platform Generic Block Timer information for the Platform.
342 ID: EArmObjPlatformGTBlockInfo
344 typedef struct CmArmGTBlockInfo
{
345 /// The physical base address for the GT Block Timer structure
346 UINT64 GTBlockPhysicalAddress
;
348 /// The number of timer frames implemented in the GT Block
349 UINT32 GTBlockTimerFrameCount
;
351 /// Reference token for the GT Block timer frame list
352 CM_OBJECT_TOKEN GTBlockTimerFrameToken
;
353 } CM_ARM_GTBLOCK_INFO
;
355 /** A structure that describes the
356 SBSA Generic Watchdog information for the Platform.
358 ID: EArmObjPlatformGenericWatchdogInfo
360 typedef struct CmArmGenericWatchdogInfo
{
361 /// The physical base address of the SBSA Watchdog control frame
362 UINT64 ControlFrameAddress
;
364 /// The physical base address of the SBSA Watchdog refresh frame
365 UINT64 RefreshFrameAddress
;
367 /// The watchdog interrupt
370 /** The flags for the watchdog as described by the SBSA watchdog
371 structure in the ACPI specification.
374 } CM_ARM_GENERIC_WATCHDOG_INFO
;
376 /** A structure that describes the
377 PCI Configuration Space information for the Platform.
379 ID: EArmObjPciConfigSpaceInfo
381 typedef struct CmArmPciConfigSpaceInfo
{
382 /// The physical base address for the PCI segment
385 /// The PCI segment group number
386 UINT16 PciSegmentGroupNumber
;
388 /// The start bus number
389 UINT8 StartBusNumber
;
391 /// The end bus number
393 } CM_ARM_PCI_CONFIG_SPACE_INFO
;
395 /** A structure that describes the
396 Hypervisor Vendor ID information for the Platform.
398 ID: EArmObjHypervisorVendorIdentity
400 typedef struct CmArmHypervisorVendorId
{
401 /// The hypervisor Vendor ID
402 UINT64 HypervisorVendorId
;
403 } CM_ARM_HYPERVISOR_VENDOR_ID
;
405 /** A structure that describes the
406 Fixed feature flags for the Platform.
408 ID: EArmObjFixedFeatureFlags
410 typedef struct CmArmFixedFeatureFlags
{
411 /// The Fixed feature flags
413 } CM_ARM_FIXED_FEATURE_FLAGS
;
415 /** A structure that describes the
416 ITS Group node for the Platform.
420 typedef struct CmArmItsGroupNode
{
421 /// An unique token used to identify this object
422 CM_OBJECT_TOKEN Token
;
423 /// The number of ITS identifiers in the ITS node
425 /// Reference token for the ITS identifier array
426 CM_OBJECT_TOKEN ItsIdToken
;
427 } CM_ARM_ITS_GROUP_NODE
;
429 /** A structure that describes the
430 GIC ITS Identifiers for an ITS Group node.
432 ID: EArmObjGicItsIdentifierArray
434 typedef struct CmArmGicItsIdentifier
{
435 /// The ITS Identifier
437 } CM_ARM_ITS_IDENTIFIER
;
439 /** A structure that describes the
440 Named component node for the Platform.
442 ID: EArmObjNamedComponent
444 typedef struct CmArmNamedComponentNode
{
445 /// An unique token used to identify this object
446 CM_OBJECT_TOKEN Token
;
447 /// Number of ID mappings
448 UINT32 IdMappingCount
;
449 /// Reference token for the ID mapping array
450 CM_OBJECT_TOKEN IdMappingToken
;
452 /// Flags for the named component
455 /// Memory access properties : Cache coherent attributes
456 UINT32 CacheCoherent
;
457 /// Memory access properties : Allocation hints
458 UINT8 AllocationHints
;
459 /// Memory access properties : Memory access flags
460 UINT8 MemoryAccessFlags
;
462 /// Memory access properties : Address size limit
463 UINT8 AddressSizeLimit
;
464 /** ASCII Null terminated string with the full path to
465 the entry in the namespace for this object.
468 } CM_ARM_NAMED_COMPONENT_NODE
;
470 /** A structure that describes the
471 Root complex node for the Platform.
473 ID: EArmObjRootComplex
475 typedef struct CmArmRootComplexNode
{
476 /// An unique token used to identify this object
477 CM_OBJECT_TOKEN Token
;
478 /// Number of ID mappings
479 UINT32 IdMappingCount
;
480 /// Reference token for the ID mapping array
481 CM_OBJECT_TOKEN IdMappingToken
;
483 /// Memory access properties : Cache coherent attributes
484 UINT32 CacheCoherent
;
485 /// Memory access properties : Allocation hints
486 UINT8 AllocationHints
;
487 /// Memory access properties : Memory access flags
488 UINT8 MemoryAccessFlags
;
492 /// PCI segment number
493 UINT32 PciSegmentNumber
;
494 /// Memory address size limit
495 UINT8 MemoryAddressSize
;
496 } CM_ARM_ROOT_COMPLEX_NODE
;
498 /** A structure that describes the
499 SMMUv1 or SMMUv2 node for the Platform.
501 ID: EArmObjSmmuV1SmmuV2
503 typedef struct CmArmSmmuV1SmmuV2Node
{
504 /// An unique token used to identify this object
505 CM_OBJECT_TOKEN Token
;
506 /// Number of ID mappings
507 UINT32 IdMappingCount
;
508 /// Reference token for the ID mapping array
509 CM_OBJECT_TOKEN IdMappingToken
;
511 /// SMMU Base Address
513 /// Length of the memory range covered by the SMMU
520 /// Number of context interrupts
521 UINT32 ContextInterruptCount
;
522 /// Reference token for the context interrupt array
523 CM_OBJECT_TOKEN ContextInterruptToken
;
525 /// Number of PMU interrupts
526 UINT32 PmuInterruptCount
;
527 /// Reference token for the PMU interrupt array
528 CM_OBJECT_TOKEN PmuInterruptToken
;
530 /// GSIV of the SMMU_NSgIrpt interrupt
532 /// SMMU_NSgIrpt interrupt flags
533 UINT32 SMMU_NSgIrptFlags
;
534 /// GSIV of the SMMU_NSgCfgIrpt interrupt
535 UINT32 SMMU_NSgCfgIrpt
;
536 /// SMMU_NSgCfgIrpt interrupt flags
537 UINT32 SMMU_NSgCfgIrptFlags
;
538 } CM_ARM_SMMUV1_SMMUV2_NODE
;
540 /** A structure that describes the
541 SMMUv3 node for the Platform.
545 typedef struct CmArmSmmuV3Node
{
546 /// An unique token used to identify this object
547 CM_OBJECT_TOKEN Token
;
548 /// Number of ID mappings
549 UINT32 IdMappingCount
;
550 /// Reference token for the ID mapping array
551 CM_OBJECT_TOKEN IdMappingToken
;
553 /// SMMU Base Address
561 /// GSIV of the Event interrupt if SPI based
562 UINT32 EventInterrupt
;
563 /// PRI Interrupt if SPI based
565 /// GERR interrupt if GSIV based
566 UINT32 GerrInterrupt
;
567 /// Sync interrupt if GSIV based
568 UINT32 SyncInterrupt
;
570 /// Proximity domain flag
571 UINT32 ProximityDomain
;
572 /// Index into the array of ID mapping
573 UINT32 DeviceIdMappingIndex
;
574 } CM_ARM_SMMUV3_NODE
;
576 /** A structure that describes the
577 PMCG node for the Platform.
581 typedef struct CmArmPmcgNode
{
582 /// An unique token used to identify this object
583 CM_OBJECT_TOKEN Token
;
584 /// Number of ID mappings
585 UINT32 IdMappingCount
;
586 /// Reference token for the ID mapping array
587 CM_OBJECT_TOKEN IdMappingToken
;
589 /// Base Address for performance monitor counter group
591 /// GSIV for the Overflow interrupt
592 UINT32 OverflowInterrupt
;
593 /// Page 1 Base address
594 UINT64 Page1BaseAddress
;
596 /// Reference token for the IORT node associated with this node
597 CM_OBJECT_TOKEN ReferenceToken
;
600 /** A structure that describes the
601 ID Mappings for the Platform.
603 ID: EArmObjIdMappingArray
605 typedef struct CmArmIdMapping
{
608 /// Number of input IDs
612 /// Reference token for the output node
613 CM_OBJECT_TOKEN OutputReferenceToken
;
618 /** A structure that describes the
619 SMMU interrupts for the Platform.
621 ID: EArmObjSmmuInterruptArray
623 typedef struct CmArmSmmuInterrupt
{
629 } CM_ARM_SMMU_INTERRUPT
;
633 #endif // ARM_NAMESPACE_OBJECTS_H_