DynamicTablesPkg/Include/ArmNameSpaceObjects.h

   1 /** @file
   2
   3   Copyright (c) 2017 - 2019, ARM Limited. All rights reserved.
   4
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7   @par Glossary:
   8     - Cm or CM   - Configuration Manager
   9     - Obj or OBJ - Object
  10     - Std or STD - Standard
  11 **/
  12
  13 #ifndef ARM_NAMESPACE_OBJECTS_H_
  14 #define ARM_NAMESPACE_OBJECTS_H_
  15
  16 #include <StandardNameSpaceObjects.h>
  17
  18 #pragma pack(1)
  19
  20 /** The EARM_OBJECT_ID enum describes the Object IDs
  21     in the ARM Namespace
  22 */
  23 typedef enum ArmObjectID {
  24   EArmObjReserved,                    ///<  0 - Reserved
  25   EArmObjBootArchInfo,                ///<  1 - Boot Architecture Info
  26   EArmObjCpuInfo,                     ///<  2 - CPU Info
  27   EArmObjPowerManagementProfileInfo,  ///<  3 - Power Management Profile Info
  28   EArmObjGicCInfo,                    ///<  4 - GIC CPU Interface Info
  29   EArmObjGicDInfo,                    ///<  5 - GIC Distributor Info
  30   EArmObjGicMsiFrameInfo,             ///<  6 - GIC MSI Frame Info
  31   EArmObjGicRedistributorInfo,        ///<  7 - GIC Redistributor Info
  32   EArmObjGicItsInfo,                  ///<  8 - GIC ITS Info
  33   EArmObjSerialConsolePortInfo,       ///<  9 - Serial Console Port Info
  34   EArmObjSerialDebugPortInfo,         ///< 10 - Serial Debug Port Info
  35   EArmObjGenericTimerInfo,            ///< 11 - Generic Timer Info
  36   EArmObjPlatformGTBlockInfo,         ///< 12 - Platform GT Block Info
  37   EArmObjGTBlockTimerFrameInfo,       ///< 13 - Generic Timer Block Frame Info
  38   EArmObjPlatformGenericWatchdogInfo, ///< 14 - Platform Generic Watchdog
  39   EArmObjPciConfigSpaceInfo,          ///< 15 - PCI Configuration Space Info
  40   EArmObjHypervisorVendorIdentity,    ///< 16 - Hypervisor Vendor Id
  41   EArmObjFixedFeatureFlags,           ///< 17 - Fixed feature flags for FADT
  42   EArmObjItsGroup,                    ///< 18 - ITS Group
  43   EArmObjNamedComponent,              ///< 19 - Named Component
  44   EArmObjRootComplex,                 ///< 20 - Root Complex
  45   EArmObjSmmuV1SmmuV2,                ///< 21 - SMMUv1 or SMMUv2
  46   EArmObjSmmuV3,                      ///< 22 - SMMUv3
  47   EArmObjPmcg,                        ///< 23 - PMCG
  48   EArmObjGicItsIdentifierArray,       ///< 24 - GIC ITS Identifier Array
  49   EArmObjIdMappingArray,              ///< 25 - ID Mapping Array
  50   EArmObjSmmuInterruptArray,          ///< 26 - SMMU Interrupt Array
  51   EArmObjProcHierarchyInfo,           ///< 27 - Processor Hierarchy Info
  52   EArmObjCacheInfo,                   ///< 28 - Cache Info
  53   EArmObjProcNodeIdInfo,              ///< 29 - Processor Hierarchy Node ID Info
  54   EArmObjCmRef,                       ///< 30 - CM Object Reference
  55   EArmObjMax
  56 } EARM_OBJECT_ID;
  57
  58 /** A structure that describes the
  59     ARM Boot Architecture flags.
  60
  61     ID: EArmObjBootArchInfo
  62 */
  63 typedef struct CmArmBootArchInfo {
  64   /** This is the ARM_BOOT_ARCH flags field of the FADT Table
  65       described in the ACPI Table Specification.
  66   */
  67   UINT32  BootArchFlags;
  68 } CM_ARM_BOOT_ARCH_INFO;
  69
  70 typedef struct CmArmCpuInfo {
  71   // Reserved for use when SMBIOS tables are implemented
  72 } CM_ARM_CPU_INFO;
  73
  74 /** A structure that describes the
  75     Power Management Profile Information for the Platform.
  76
  77     ID: EArmObjPowerManagementProfileInfo
  78 */
  79 typedef struct CmArmPowerManagementProfileInfo {
  80   /** This is the Preferred_PM_Profile field of the FADT Table
  81       described in the ACPI Specification
  82   */
  83   UINT8  PowerManagementProfile;
  84 } CM_ARM_POWER_MANAGEMENT_PROFILE_INFO;
  85
  86 /** A structure that describes the
  87     GIC CPU Interface for the Platform.
  88
  89     ID: EArmObjGicCInfo
  90 */
  91 typedef struct CmArmGicCInfo {
  92   /// The GIC CPU Interface number.
  93   UINT32  CPUInterfaceNumber;
  94
  95   /** The ACPI Processor UID. This must match the
  96       _UID of the CPU Device object information described
  97       in the DSDT/SSDT for the CPU.
  98   */
  99   UINT32  AcpiProcessorUid;
 100
 101   /** The flags field as described by the GICC structure
 102       in the ACPI Specification.
 103   */
 104   UINT32  Flags;
 105
 106   /** The parking protocol version field as described by
 107     the GICC structure in the ACPI Specification.
 108   */
 109   UINT32  ParkingProtocolVersion;
 110
 111   /** The Performance Interrupt field as described by
 112       the GICC structure in the ACPI Specification.
 113   */
 114   UINT32  PerformanceInterruptGsiv;
 115
 116   /** The CPU Parked address field as described by
 117       the GICC structure in the ACPI Specification.
 118   */
 119   UINT64  ParkedAddress;
 120
 121   /** The base address for the GIC CPU Interface
 122       as described by the GICC structure in the
 123       ACPI Specification.
 124   */
 125   UINT64  PhysicalBaseAddress;
 126
 127   /** The base address for GICV interface
 128       as described by the GICC structure in the
 129       ACPI Specification.
 130   */
 131   UINT64  GICV;
 132
 133   /** The base address for GICH interface
 134       as described by the GICC structure in the
 135       ACPI Specification.
 136   */
 137   UINT64  GICH;
 138
 139   /** The GICV maintenance interrupt
 140       as described by the GICC structure in the
 141       ACPI Specification.
 142   */
 143   UINT32  VGICMaintenanceInterrupt;
 144
 145   /** The base address for GICR interface
 146       as described by the GICC structure in the
 147       ACPI Specification.
 148   */
 149   UINT64  GICRBaseAddress;
 150
 151   /** The MPIDR for the CPU
 152       as described by the GICC structure in the
 153       ACPI Specification.
 154   */
 155   UINT64  MPIDR;
 156
 157   /** The Processor Power Efficiency class
 158       as described by the GICC structure in the
 159       ACPI Specification.
 160   */
 161   UINT8   ProcessorPowerEfficiencyClass;
 162
 163   /** Statistical Profiling Extension buffer overflow GSIV. Zero if
 164       unsupported by this processor. This field was introduced in
 165       ACPI 6.3 (MADT revision 5) and is therefore ignored when
 166       generating MADT revision 4 or lower.
 167   */
 168   UINT16  SpeOverflowInterrupt;
 169 } CM_ARM_GICC_INFO;
 170
 171 /** A structure that describes the
 172     GIC Distributor information for the Platform.
 173
 174     ID: EArmObjGicDInfo
 175 */
 176 typedef struct CmArmGicDInfo {
 177   /// The Physical Base address for the GIC Distributor.
 178   UINT64  PhysicalBaseAddress;
 179
 180   /** The global system interrupt
 181       number where this GIC Distributor's
 182       interrupt inputs start.
 183   */
 184   UINT32  SystemVectorBase;
 185
 186   /** The GIC version as described
 187       by the GICD structure in the
 188       ACPI Specification.
 189   */
 190   UINT8   GicVersion;
 191 } CM_ARM_GICD_INFO;
 192
 193 /** A structure that describes the
 194     GIC MSI Frame information for the Platform.
 195
 196     ID: EArmObjGicMsiFrameInfo
 197 */
 198 typedef struct CmArmGicMsiFrameInfo {
 199   /// The GIC MSI Frame ID
 200   UINT32  GicMsiFrameId;
 201
 202   /// The Physical base address for the MSI Frame
 203   UINT64  PhysicalBaseAddress;
 204
 205   /** The GIC MSI Frame flags
 206       as described by the GIC MSI frame
 207       structure in the ACPI Specification.
 208   */
 209   UINT32  Flags;
 210
 211   /// SPI Count used by this frame
 212   UINT16  SPICount;
 213
 214   /// SPI Base used by this frame
 215   UINT16  SPIBase;
 216 } CM_ARM_GIC_MSI_FRAME_INFO;
 217
 218 /** A structure that describes the
 219     GIC Redistributor information for the Platform.
 220
 221     ID: EArmObjGicRedistributorInfo
 222 */
 223 typedef struct CmArmGicRedistInfo {
 224   /** The physical address of a page range
 225       containing all GIC Redistributors.
 226   */
 227   UINT64  DiscoveryRangeBaseAddress;
 228
 229   /// Length of the GIC Redistributor Discovery page range
 230   UINT32  DiscoveryRangeLength;
 231 } CM_ARM_GIC_REDIST_INFO;
 232
 233 /** A structure that describes the
 234     GIC Interrupt Translation Service information for the Platform.
 235
 236     ID: EArmObjGicItsInfo
 237 */
 238 typedef struct CmArmGicItsInfo {
 239   /// The GIC ITS ID
 240   UINT32  GicItsId;
 241
 242   /// The physical address for the Interrupt Translation Service
 243   UINT64  PhysicalBaseAddress;
 244 } CM_ARM_GIC_ITS_INFO;
 245
 246 /** A structure that describes the
 247     Serial Port information for the Platform.
 248
 249     ID: EArmObjSerialConsolePortInfo or
 250         EArmObjSerialDebugPortInfo
 251 */
 252 typedef struct CmArmSerialPortInfo {
 253   /// The physical base address for the serial port
 254   UINT64  BaseAddress;
 255
 256   /// The serial port interrupt
 257   UINT32  Interrupt;
 258
 259   /// The serial port baud rate
 260   UINT64  BaudRate;
 261
 262   /// The serial port clock
 263   UINT32  Clock;
 264
 265   /// Serial Port subtype
 266   UINT16  PortSubtype;
 267 } CM_ARM_SERIAL_PORT_INFO;
 268
 269 /** A structure that describes the
 270     Generic Timer information for the Platform.
 271
 272     ID: EArmObjGenericTimerInfo
 273 */
 274 typedef struct CmArmGenericTimerInfo {
 275   /// The physical base address for the counter control frame
 276   UINT64  CounterControlBaseAddress;
 277
 278   /// The physical base address for the counter read frame
 279   UINT64  CounterReadBaseAddress;
 280
 281   /// The secure PL1 timer interrupt
 282   UINT32  SecurePL1TimerGSIV;
 283
 284   /// The secure PL1 timer flags
 285   UINT32  SecurePL1TimerFlags;
 286
 287   /// The non-secure PL1 timer interrupt
 288   UINT32  NonSecurePL1TimerGSIV;
 289
 290   /// The non-secure PL1 timer flags
 291   UINT32  NonSecurePL1TimerFlags;
 292
 293   /// The virtual timer interrupt
 294   UINT32  VirtualTimerGSIV;
 295
 296   /// The virtual timer flags
 297   UINT32  VirtualTimerFlags;
 298
 299   /// The non-secure PL2 timer interrupt
 300   UINT32  NonSecurePL2TimerGSIV;
 301
 302   /// The non-secure PL2 timer flags
 303   UINT32  NonSecurePL2TimerFlags;
 304 } CM_ARM_GENERIC_TIMER_INFO;
 305
 306 /** A structure that describes the
 307     Platform Generic Block Timer Frame information for the Platform.
 308
 309     ID: EArmObjGTBlockTimerFrameInfo
 310 */
 311 typedef struct CmArmGTBlockTimerFrameInfo {
 312   /// The Generic Timer frame number
 313   UINT8   FrameNumber;
 314
 315   /// The physical base address for the CntBase block
 316   UINT64  PhysicalAddressCntBase;
 317
 318   /// The physical base address for the CntEL0Base block
 319   UINT64  PhysicalAddressCntEL0Base;
 320
 321   /// The physical timer interrupt
 322   UINT32  PhysicalTimerGSIV;
 323
 324   /** The physical timer flags as described by the GT Block
 325       Timer frame Structure in the ACPI Specification.
 326   */
 327   UINT32  PhysicalTimerFlags;
 328
 329   /// The virtual timer interrupt
 330   UINT32  VirtualTimerGSIV;
 331
 332   /** The virtual timer flags as described by the GT Block
 333       Timer frame Structure in the ACPI Specification.
 334   */
 335   UINT32  VirtualTimerFlags;
 336
 337   /** The common timer flags as described by the GT Block
 338       Timer frame Structure in the ACPI Specification.
 339   */
 340   UINT32  CommonFlags;
 341 } CM_ARM_GTBLOCK_TIMER_FRAME_INFO;
 342
 343 /** A structure that describes the
 344     Platform Generic Block Timer information for the Platform.
 345
 346     ID: EArmObjPlatformGTBlockInfo
 347 */
 348 typedef struct CmArmGTBlockInfo {
 349   /// The physical base address for the GT Block Timer structure
 350   UINT64            GTBlockPhysicalAddress;
 351
 352   /// The number of timer frames implemented in the GT Block
 353   UINT32            GTBlockTimerFrameCount;
 354
 355   /// Reference token for the GT Block timer frame list
 356   CM_OBJECT_TOKEN   GTBlockTimerFrameToken;
 357 } CM_ARM_GTBLOCK_INFO;
 358
 359 /** A structure that describes the
 360     SBSA Generic Watchdog information for the Platform.
 361
 362     ID: EArmObjPlatformGenericWatchdogInfo
 363 */
 364 typedef struct CmArmGenericWatchdogInfo {
 365   /// The physical base address of the SBSA Watchdog control frame
 366   UINT64  ControlFrameAddress;
 367
 368   /// The physical base address of the SBSA Watchdog refresh frame
 369   UINT64  RefreshFrameAddress;
 370
 371   /// The watchdog interrupt
 372   UINT32  TimerGSIV;
 373
 374   /** The flags for the watchdog as described by the SBSA watchdog
 375       structure in the ACPI specification.
 376   */
 377   UINT32  Flags;
 378 } CM_ARM_GENERIC_WATCHDOG_INFO;
 379
 380 /** A structure that describes the
 381     PCI Configuration Space information for the Platform.
 382
 383     ID: EArmObjPciConfigSpaceInfo
 384 */
 385 typedef struct CmArmPciConfigSpaceInfo {
 386   /// The physical base address for the PCI segment
 387   UINT64  BaseAddress;
 388
 389   /// The PCI segment group number
 390   UINT16  PciSegmentGroupNumber;
 391
 392   /// The start bus number
 393   UINT8   StartBusNumber;
 394
 395   /// The end bus number
 396   UINT8   EndBusNumber;
 397 } CM_ARM_PCI_CONFIG_SPACE_INFO;
 398
 399 /** A structure that describes the
 400     Hypervisor Vendor ID information for the Platform.
 401
 402     ID: EArmObjHypervisorVendorIdentity
 403 */
 404 typedef struct CmArmHypervisorVendorId {
 405   /// The hypervisor Vendor ID
 406   UINT64  HypervisorVendorId;
 407 } CM_ARM_HYPERVISOR_VENDOR_ID;
 408
 409 /** A structure that describes the
 410     Fixed feature flags for the Platform.
 411
 412     ID: EArmObjFixedFeatureFlags
 413 */
 414 typedef struct CmArmFixedFeatureFlags {
 415   /// The Fixed feature flags
 416   UINT32  Flags;
 417 } CM_ARM_FIXED_FEATURE_FLAGS;
 418
 419 /** A structure that describes the
 420     ITS Group node for the Platform.
 421
 422     ID: EArmObjItsGroup
 423 */
 424 typedef struct CmArmItsGroupNode {
 425   /// An unique token used to identify this object
 426   CM_OBJECT_TOKEN   Token;
 427   /// The number of ITS identifiers in the ITS node
 428   UINT32            ItsIdCount;
 429   /// Reference token for the ITS identifier array
 430   CM_OBJECT_TOKEN   ItsIdToken;
 431 } CM_ARM_ITS_GROUP_NODE;
 432
 433 /** A structure that describes the
 434     GIC ITS Identifiers for an ITS Group node.
 435
 436     ID: EArmObjGicItsIdentifierArray
 437 */
 438 typedef struct CmArmGicItsIdentifier {
 439   /// The ITS Identifier
 440   UINT32  ItsId;
 441 } CM_ARM_ITS_IDENTIFIER;
 442
 443 /** A structure that describes the
 444     Named component node for the Platform.
 445
 446     ID: EArmObjNamedComponent
 447 */
 448 typedef struct CmArmNamedComponentNode {
 449   /// An unique token used to identify this object
 450   CM_OBJECT_TOKEN   Token;
 451   /// Number of ID mappings
 452   UINT32            IdMappingCount;
 453   /// Reference token for the ID mapping array
 454   CM_OBJECT_TOKEN   IdMappingToken;
 455
 456   /// Flags for the named component
 457   UINT32            Flags;
 458
 459   /// Memory access properties : Cache coherent attributes
 460   UINT32            CacheCoherent;
 461   /// Memory access properties : Allocation hints
 462   UINT8             AllocationHints;
 463   /// Memory access properties : Memory access flags
 464   UINT8             MemoryAccessFlags;
 465
 466   /// Memory access properties : Address size limit
 467   UINT8             AddressSizeLimit;
 468   /** ASCII Null terminated string with the full path to
 469       the entry in the namespace for this object.
 470   */
 471   CHAR8*            ObjectName;
 472 } CM_ARM_NAMED_COMPONENT_NODE;
 473
 474 /** A structure that describes the
 475     Root complex node for the Platform.
 476
 477     ID: EArmObjRootComplex
 478 */
 479 typedef struct CmArmRootComplexNode {
 480   /// An unique token used to identify this object
 481   CM_OBJECT_TOKEN   Token;
 482   /// Number of ID mappings
 483   UINT32            IdMappingCount;
 484   /// Reference token for the ID mapping array
 485   CM_OBJECT_TOKEN   IdMappingToken;
 486
 487   /// Memory access properties : Cache coherent attributes
 488   UINT32            CacheCoherent;
 489   /// Memory access properties : Allocation hints
 490   UINT8             AllocationHints;
 491   /// Memory access properties : Memory access flags
 492   UINT8             MemoryAccessFlags;
 493
 494   /// ATS attributes
 495   UINT32            AtsAttribute;
 496   /// PCI segment number
 497   UINT32            PciSegmentNumber;
 498   /// Memory address size limit
 499   UINT8             MemoryAddressSize;
 500 } CM_ARM_ROOT_COMPLEX_NODE;
 501
 502 /** A structure that describes the
 503     SMMUv1 or SMMUv2 node for the Platform.
 504
 505     ID: EArmObjSmmuV1SmmuV2
 506 */
 507 typedef struct CmArmSmmuV1SmmuV2Node {
 508   /// An unique token used to identify this object
 509   CM_OBJECT_TOKEN   Token;
 510   /// Number of ID mappings
 511   UINT32            IdMappingCount;
 512   /// Reference token for the ID mapping array
 513   CM_OBJECT_TOKEN   IdMappingToken;
 514
 515   /// SMMU Base Address
 516   UINT64            BaseAddress;
 517   /// Length of the memory range covered by the SMMU
 518   UINT64            Span;
 519   /// SMMU Model
 520   UINT32            Model;
 521   /// SMMU flags
 522   UINT32            Flags;
 523
 524   /// Number of context interrupts
 525   UINT32            ContextInterruptCount;
 526   /// Reference token for the context interrupt array
 527   CM_OBJECT_TOKEN   ContextInterruptToken;
 528
 529   /// Number of PMU interrupts
 530   UINT32            PmuInterruptCount;
 531   /// Reference token for the PMU interrupt array
 532   CM_OBJECT_TOKEN   PmuInterruptToken;
 533
 534   /// GSIV of the SMMU_NSgIrpt interrupt
 535   UINT32            SMMU_NSgIrpt;
 536   /// SMMU_NSgIrpt interrupt flags
 537   UINT32            SMMU_NSgIrptFlags;
 538   /// GSIV of the SMMU_NSgCfgIrpt interrupt
 539   UINT32            SMMU_NSgCfgIrpt;
 540   /// SMMU_NSgCfgIrpt interrupt flags
 541   UINT32            SMMU_NSgCfgIrptFlags;
 542 } CM_ARM_SMMUV1_SMMUV2_NODE;
 543
 544 /** A structure that describes the
 545     SMMUv3 node for the Platform.
 546
 547     ID: EArmObjSmmuV3
 548 */
 549 typedef struct CmArmSmmuV3Node {
 550   /// An unique token used to identify this object
 551   CM_OBJECT_TOKEN   Token;
 552   /// Number of ID mappings
 553   UINT32            IdMappingCount;
 554   /// Reference token for the ID mapping array
 555   CM_OBJECT_TOKEN   IdMappingToken;
 556
 557   /// SMMU Base Address
 558   UINT64    BaseAddress;
 559   /// SMMU flags
 560   UINT32            Flags;
 561   /// VATOS address
 562   UINT64            VatosAddress;
 563   /// Model
 564   UINT32            Model;
 565   /// GSIV of the Event interrupt if SPI based
 566   UINT32            EventInterrupt;
 567   /// PRI Interrupt if SPI based
 568   UINT32            PriInterrupt;
 569   /// GERR interrupt if GSIV based
 570   UINT32            GerrInterrupt;
 571   /// Sync interrupt if GSIV based
 572   UINT32            SyncInterrupt;
 573
 574   /// Proximity domain flag
 575   UINT32            ProximityDomain;
 576   /// Index into the array of ID mapping
 577   UINT32            DeviceIdMappingIndex;
 578 } CM_ARM_SMMUV3_NODE;
 579
 580 /** A structure that describes the
 581     PMCG node for the Platform.
 582
 583     ID: EArmObjPmcg
 584 */
 585 typedef struct CmArmPmcgNode {
 586   /// An unique token used to identify this object
 587   CM_OBJECT_TOKEN   Token;
 588   /// Number of ID mappings
 589   UINT32            IdMappingCount;
 590   /// Reference token for the ID mapping array
 591   CM_OBJECT_TOKEN   IdMappingToken;
 592
 593   /// Base Address for performance monitor counter group
 594   UINT64            BaseAddress;
 595   /// GSIV for the Overflow interrupt
 596   UINT32            OverflowInterrupt;
 597   /// Page 1 Base address
 598   UINT64            Page1BaseAddress;
 599
 600   /// Reference token for the IORT node associated with this node
 601   CM_OBJECT_TOKEN   ReferenceToken;
 602 } CM_ARM_PMCG_NODE;
 603
 604 /** A structure that describes the
 605     ID Mappings for the Platform.
 606
 607     ID: EArmObjIdMappingArray
 608 */
 609 typedef struct CmArmIdMapping {
 610   /// Input base
 611   UINT32           InputBase;
 612   /// Number of input IDs
 613   UINT32           NumIds;
 614   /// Output Base
 615   UINT32           OutputBase;
 616   /// Reference token for the output node
 617   CM_OBJECT_TOKEN  OutputReferenceToken;
 618   /// Flags
 619   UINT32    Flags;
 620 } CM_ARM_ID_MAPPING;
 621
 622 /** A structure that describes the
 623     SMMU interrupts for the Platform.
 624
 625     ID: EArmObjSmmuInterruptArray
 626 */
 627 typedef struct CmArmSmmuInterrupt {
 628   /// Interrupt number
 629   UINT32    Interrupt;
 630
 631   /// Flags
 632   UINT32    Flags;
 633 } CM_ARM_SMMU_INTERRUPT;
 634
 635 /** A structure that describes the Processor Hierarchy Node (Type 0) in PPTT
 636
 637     ID: EArmObjProcHierarchyInfo
 638 */
 639 typedef struct CmArmProcHierarchyInfo {
 640   /// A unique token used to identify this object
 641   CM_OBJECT_TOKEN   Token;
 642   /// Processor structure flags (ACPI 6.3 - January 2019, PPTT, Table 5-155)
 643   UINT32            Flags;
 644   /// Token for the parent CM_ARM_PROC_HIERARCHY_INFO object in the processor
 645   /// topology. A value of CM_NULL_TOKEN means this node has no parent.
 646   CM_OBJECT_TOKEN   ParentToken;
 647   /// Token of the associated CM_ARM_GICC_INFO object which has the
 648   /// corresponding ACPI Processor ID. A value of CM_NULL_TOKEN means this
 649   /// node represents a group of associated processors and it does not have an
 650   /// associated GIC CPU interface.
 651   CM_OBJECT_TOKEN   GicCToken;
 652   /// Number of resources private to this Node
 653   UINT32            NoOfPrivateResources;
 654   /// Token of the array which contains references to the resources private to
 655   /// this CM_ARM_PROC_HIERARCHY_INFO instance. This field is ignored if
 656   /// the NoOfPrivateResources is 0, in which case it is recomended to set
 657   /// this field to CM_NULL_TOKEN.
 658   CM_OBJECT_TOKEN   PrivateResourcesArrayToken;
 659 } CM_ARM_PROC_HIERARCHY_INFO;
 660
 661 /** A structure that describes the Cache Type Structure (Type 1) in PPTT
 662
 663     ID: EArmObjCacheInfo
 664 */
 665 typedef struct CmArmCacheInfo {
 666   /// A unique token used to identify this object
 667   CM_OBJECT_TOKEN   Token;
 668   /// Reference token for the next level of cache that is private to the same
 669   /// CM_ARM_PROC_HIERARCHY_INFO instance. A value of CM_NULL_TOKEN means this
 670   /// entry represents the last cache level appropriate to the processor
 671   /// hierarchy node structures using this entry.
 672   CM_OBJECT_TOKEN   NextLevelOfCacheToken;
 673   /// Size of the cache in bytes
 674   UINT32            Size;
 675   /// Number of sets in the cache
 676   UINT32            NumberOfSets;
 677   /// Integer number of ways. The maximum associativity supported by
 678   /// ACPI Cache type structure is limited to MAX_UINT8. However,
 679   /// the maximum number of ways supported by the architecture is
 680   /// PPTT_ARM_CCIDX_CACHE_ASSOCIATIVITY_MAX. Therfore this field
 681   /// is 32-bit wide.
 682   UINT32            Associativity;
 683   /// Cache attributes (ACPI 6.3 - January 2019, PPTT, Table 5-156)
 684   UINT8             Attributes;
 685   /// Line size in bytes
 686   UINT16            LineSize;
 687 } CM_ARM_CACHE_INFO;
 688
 689 /** A structure that describes the ID Structure (Type 2) in PPTT
 690
 691     ID: EArmObjProcNodeIdInfo
 692 */
 693 typedef struct CmArmProcNodeIdInfo {
 694   /// A unique token used to identify this object
 695   CM_OBJECT_TOKEN   Token;
 696   // Vendor ID (as described in ACPI ID registry)
 697   UINT32            VendorId;
 698   /// First level unique node ID
 699   UINT64            Level1Id;
 700   /// Second level unique node ID
 701   UINT64            Level2Id;
 702   /// Major revision of the node
 703   UINT16            MajorRev;
 704   /// Minor revision of the node
 705   UINT16            MinorRev;
 706   /// Spin revision of the node
 707   UINT16            SpinRev;
 708 } CM_ARM_PROC_NODE_ID_INFO;
 709
 710 /** A structure that describes a reference to another Configuration Manager
 711     object.
 712
 713     This is useful for creating an array of reference tokens. The framework
 714     can then query the configuration manager for these arrays using the
 715     object ID EArmObjCmRef.
 716
 717     This can be used is to represent one-to-many relationships between objects.
 718
 719     ID: EArmObjCmRef
 720 */
 721 typedef struct CmArmObjRef {
 722   /// Token of the CM object being referenced
 723   CM_OBJECT_TOKEN   ReferenceToken;
 724 } CM_ARM_OBJ_REF;
 725
 726 #pragma pack()
 727
 728 #endif // ARM_NAMESPACE_OBJECTS_H_